Kalle Kivekäs

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-/spl mu/m BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively.

2.4-GHz receiver for sensor applications

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.

Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-/spl mu/m SiGe BiCMOS process and is characterized at 900 MHz.

A direct conversion RF front-end for 2-GHz WCDMA and 5.8-GHz WLAN applications

A direct conversion RF front-end for 2.0 GHz WCDMA and 5.8 GHz WLAN applications is described. The measured double-sideband NF, IIP3 and voltage gain are 3.6 dB, -15.1 dBm and 29.5 dB for WCDMA, and 5.2 dB, -17.4 dBm and 26.5 dB for WLAN, respectively. The RF front-end consumes 22.3 mA in WCDMA mode and 23.1 mA in WLAN mode from a 2.7 V supply. The chip is fabricated using a 0.35 /spl mu/m 45 GHz SiGe BiCMOS process.

Design of low-voltage active mixer for direct conversion receivers

Evolution and design trade-offs of a high performance, low-voltage downconversion mixer for wireless direct conversion receivers (DCR) are studied in this paper. As a first step, a mixer with active loads and adjustable conversion gain is presented. Then a different mixer topology that provides high conversion gain without deteriorating the linearity and noise performance is discussed. Finally, this topology is found to be well suitable for very low-voltage applications and thus its design and voltage scalability is depicted. The presented mixers are designed using a 0.35-/spl mu/m BiCMOS process and characterized at 2 GHz frequency.

An IIP2 calibration technique for direct conversion receivers

An improvement for a previously published IIP2 calibration method for a Gilbert cell type mixer is introduced. In the previous solution the IIP2 was degraded as a function of the baseband frequency when a mixer with RC load was used. This solution maintains a high IIP2 over the entire baseband channel in wideband systems. In order to implement an on-chip tuning engine the correct trimming code has to be detected. Two different solutions for the detection of the correct trimming code are discussed in this paper.

Dual-mode direct-conversion RF receiver with IIP2 calibration

A single-chip dual-mode direct-conversion RF receiver with an improved method for increasing the IIP2 of the downconversion mixer is described. An improved IIP2 over the 2-MHz baseband channel is achieved. The 0.35-/spl mu/m SiGe BiCMOS RF receiver achieves 3.2-dB NF and -13-dBm IIP3 in 2-GHz mode, and 7.4-dB NF and -17-dBm IIP3 in 5-GHz mode. The current consumption in 2-GHz mode is 29.6 mA and in 5-GHz mode 28.4 mA. The chip area is 5.1 mm/sup 2/.

A wide-band direct conversion receiver with on-chip A/D converters

In wireless communications, the receiver architectures, which have on-chip channel selection filters like direct conversion or low-IF, are preferred to increase the integration level. Combining digital signal processing on the same chip with analog circuits would be desirable in the miniaturization. Some recent papers present highly integrated tranceivers with mixed-mode or digital circuits on the same chip. However, only little discussion or experimental results have been given on the potential problems related to the system. This paper focuses on the design aspects of the single-chip direct conversion receivers, and gives experimental results of the BiCMOS prototype. The chip includes RF front-end, analog baseband signal processing and 6-bit A/D converters on the same die. It operates in the third generation wideband CDMA wireless system at 2 GHz.

RF gain control in direct conversion receivers

This paper presents a study of LO self-mixing and RF gain control issues in direct conversion receivers. In cellular systems, that use continuous time frequency duplexing, these can constitute serious problems. The presented topic is of special importance when digitally programmable gain is implemented at the RF frequencies before the downconversion mixers, practically in the LNA. Furthermore, this paper gives circuit solutions to overcome this problem.

Active Mixers for Direct Conversion Receivers with 0.35- \bimu m BiCMOS

In this paper, the design requirements of different mixers for direct conversion receivers are discussed. Special attention has been paid into the detection of amplitude-modulated RF signal envelope. Three active mixers have been implemented to investigate the discussed requirements by using a 0.35-μm, 25-GHz BiCMOS technology. The same process allows an objective comparison between the different topologies. The mixers are designed for a single 2.7 V supply, and specified for low power consumption. Different topologies are compared by their spurious free dynamic ranges (SFDR) with respect to their individual power consumption. Also, their performance were measured at different LO power levels and supply voltages. The results show insignificant differences between the topologies in low voltage applications.