Jouni Kaukovuori

Analysis and Design of Passive Polyphase Filters

Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

Multitone Fast Frequency-Hopping Synthesizer for UWB Radio

A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it offers operation in mandatory band group 1 and in extensional band group 3. The circuit entity consists of three parallel phase-locked loops (PLLs), each including two voltage-controlled oscillators, one per band group, and a signal multiplexer for fast frequency selection. A broadband poly-phase RC filter is used for in-phase/quadrature generation. Furthermore, the synthesizer generates the clock signal for analog-to-digital converters by mixing the signals from the first and third PLL. The circuit was fabricated in a 0.13- mum CMOS process and it consumes 32 mA from a 1.2-V supply. It achieves 2-ns frequency settling time with a 3-MHz hopping rate.

A direct conversion RF front-end for 2-GHz WCDMA and 5.8-GHz WLAN applications

A direct conversion RF front-end for 2.0 GHz WCDMA and 5.8 GHz WLAN applications is described. The measured double-sideband NF, IIP3 and voltage gain are 3.6 dB, -15.1 dBm and 29.5 dB for WCDMA, and 5.2 dB, -17.4 dBm and 26.5 dB for WLAN, respectively. The RF front-end consumes 22.3 mA in WCDMA mode and 23.1 mA in WLAN mode from a 2.7 V supply. The chip is fabricated using a 0.35 /spl mu/m 45 GHz SiGe BiCMOS process.

2.4-GHz receiver for sensor applications

In this paper, a 3.4-mW direct-conversion receiver, operating at 2.4 GHz, is presented. The receiver includes merged low-noise amplifier and quadrature mixers, local oscillator buffers, and one analog baseband channel. The 0.13-/spl mu/m CMOS receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.

Dual-mode direct-conversion RF receiver with IIP2 calibration

A single-chip dual-mode direct-conversion RF receiver with an improved method for increasing the IIP2 of the downconversion mixer is described. An improved IIP2 over the 2-MHz baseband channel is achieved. The 0.35-/spl mu/m SiGe BiCMOS RF receiver achieves 3.2-dB NF and -13-dBm IIP3 in 2-GHz mode, and 7.4-dB NF and -17-dBm IIP3 in 5-GHz mode. The current consumption in 2-GHz mode is 29.6 mA and in 5-GHz mode 28.4 mA. The chip area is 5.1 mm/sup 2/.

A Dual-Band Direct-Conversion RF Front-End for WiMedia UWB Receiver

This paper describes a direct-conversion RF front-end designed for dual-band WiMedia UWB receiver. The front-end operates in band groups BG1 and BG3. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. As targeted for mobile handset, several issues related to hostile environment are taken into account in this design. The front-end achieves approximately 26-dB gain and 4.9 to 5.6-dB noise figure (NF) across three subbands of BG1. In BG3 mode it obtains 23 - 26-dB gain and 6.9 to 7.7-dB NF. The front-end consumes 48.1 mA and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-mum CMOS.

CMOS Low-Noise Amplifier Analysis and Optimization for Wideband Applications

A low-noise amplifier design for the wideband applications is discussed in this paper. A typical inductively degenerated common source (IDCS) LNA is optimal for narrowband systems with reception band of few hundred MHz. However, ultrawideband systems with multiple GHz bandwidth set new requirements for the LNA. In this paper the usability of IDCS topology for UWB system is studied. Different possibilities to enhance bandwidth without using extra inductors are analyzed and compared

Analysis of different feedback topologies to LNA input matching

This paper describes the analysis of different feedback topologies to LNA input matching. The effect of different components to LNA input impedance is discussed. Analyzed feedback topologies can also be used to eliminate the source inductor found in IDCS LNA and feedback can be used to achieve matching in packaged LNA where the bond wire is no longer a free design parameter. A design example, using a 1.2-V 65-nm CMOS process, is given for a packaged LNA to demonstrate that adequate performance can be achieved using the presented theory and topologies.

Direct-conversion receiver for ubiquitous communications

A direct-conversion receiver for a 2.4-GHz sensor network is described. The receiver is designed to operate in a Bluetooth system where slight changes are made in the radio parameters to meet the low power requirement. The receiver includes an LNA, downconversion mixers, a 90-degree phase shift circuit, analog filters, a 1-bit analog-to-digital converter, and a received signal strength indicator (RSSI). The receiver consumes 4.1 mA from a 1.2-V power supply and it achieves 43-dB voltage gain, 25-dB noise figure, -22-dBm IIP3, and +11-dBm IIP2.

A Direct-Conversion RF Front-End in a 65-nm CMOS

A 2.4-GHz direct-conversion RF front-end designed in a 65-nm CMOS process is described in this paper. The front-end includes an LNA, folded quadrature mixers, a local oscillator (LO) divider, and LO buffers. The front-end consumes 29.3 mA from a 1.2-V power supply and according to simulations it achieves 39-dB voltage gain, 1.5-dB minimum spot noise figure, and -17-dBm IIP3