Tien-Yen Wang

A low power phase change memory using thermally confined TaN/TiN bottom electrode

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications

The large performance gap between traditional storage and the rest of the memory hierarchy calls for a storage class memory (SCM) to fill the need. Phase change memory (PCM) is an emerging memory candidate for SCM with the advantages of scalability, bit-alterability, non-volatility, and high program speed. Previous publications demonstrated high-density single-level-cell (SLC) PCMs using circuits and architectural techniques for expanding memory capacity, increasing bandwidth, and enabling embedded applications [1-4]. For PCM to be a true contender, a multi-level-cell (MLC) topology with at least a moderate data retention time is required. However, the resistance-drift (R-drift) effect causes cell resistance (RCELL) to increase with time, exceeding the ECC correction ability within hours of being programmed. Conventional R-drift mitigation approaches using reference-cell-based resistance tracking (RCRT) [5] and DRAM-like refresh (DR) [6] are feasible, but at the cost of compromising distinguished PCM traits: random write, low latency, and low power. This paper proposes a resistance drift compensation (RDC) scheme to mitigate against R-drift without such compromises, while minimizing the speed and power consumption penalties. The MLC-PCM fixed-threshold retention (FTR) raw-bit-error-rate (RBER) has been suppressed by over two orders of magnitude, reducing it below practical ECC capability limits.

A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications

A novel Cycle Alarm Point (CAP) inspection is proposed to monitor PCM cycling degradation. The degradation appears in two stages - (1) right shift of R-I during moderate cycling degradation, and (2) left shift of R-I when cycling damage is severe. We further propose an In-Situ-Self-Anneal (ISSA) procedure, such that once a CAP signal is detected, the annealing procedure is issued to rejuvenate the cells. We demonstrate, for the first time, PCM cycling degradation can be recovered repeatedly. This opens a new window to extend PCM endurance and reliability for storage class memory (SCM) applications.

Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme

Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three independent 10X sensing windows (100KΩ~1MΩ × 3) all on same read speed. Each sensing window only needs to store 2~3 resistance levels instead of 8 levels needed in conventional MLC method, thus can tolerate resistance drift without closing the memory windows. A maximum of 16 levels of MLC is demonstrated on a 256Mb chip that is suitable for 4-bits/cell application.

A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances

Inherent cell variation of phase change memory is difficult to control by material or device engineering alone. We previously reported R-I curve shift detection scheme as a good method for monitoring PCM cell characteristics. This paper extends that concept and proposes a Stress-trim procedure to tighten R-I characteristics for PCM MLC operation. By leveraging the right-shift phenomena of PCM R-I curves, we demonstrated that Stress-trim can effectively reduce cell variation to improve MLC performance. A MLC program current amplitude range reduction of 40% and MLC time to failure extension of nearly 150X are achieved.

Optimization of programming current on endurance of phase change memory

We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over

For multilevel cell (MLC) phase change memory (PCM), resistance drift (R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100×, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.

100\times

Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.

for Storage Class Memory Applications

Operation impact on endurance performance in GST-based phase change memory is investigated from small arrays to large test chips. SET operation induced electromigration and phase segregation are observed. For the first time, the RESET melting healing effect is proposed to partially repair the SET induced damage and further extend the endurance. This concept can be easily implemented by accordingly designing the control circuits.

A double-density dual-mode phase change memory using a novel background storage scheme

TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.