King-Chang Shu

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

Study of mask corner rounding effects on lithographic patterning for 90-nm technology node and beyond

This paper presented an integrated simulation framework linking our in-house mask writer simulator and the optical lithography simulation engines to include the mask corner rounding effect in lithographic performance evaluations. In the writer simulator, a modified two-dimensional Gaussian function is used as the functional form of the convolution kernel (point spread function). Parameters of the kernel function for different writing machines are automatically extracted from scanning electron microscope (SEM) photographs of simple mask pattern geometries. The convolution results of the kernel and the mask layout form the intensity distribution for pattern definition. The isocontour of the resulting image at the desired level of bias can be regarded as a good approximation of the mask shape obtained from a real mask writer. The writer simulator then saves the contour data as the user-specified format of mask file for subsequent lithography simulations. With the aid of this simulation tool, the impacts of mask corner rounding effects on two-dimensional OPCed pattern for 90-nm and 65-nm node lithography processes are quantitatively evaluated. The results show the line end shortening (LES) is greatly influenced by mask corner rounding effects. The LESs in the 65-nm node process are over twice of those in the 90-nm node process. The resolution capability of a 2-stage 16X mask manufacturing process was also studied in this paper. Simulation results indicate the ArF lithography might be required to make this innovative mask-making technology suitable for 90-nm generation and beyond.

Phase-defocus windows for alternating phase shifting mask

We propose a useful methodology, called phase-defocus (P-D) window, to express the mutual dependence of Alt-PSM mask structure and the wafer process window of the pattern-position shift caused by phase error and intensity imbalance. The P-D window was predicted and optimized with a 2-D mask with effective phase and transmission by simulations. We further used rigorous E-M field simulations to correlate the 3-D mask structure to those optimized conditions. Moreover, experiments were performed with four kinds of mask structures and the best Alt-PSM structure was obtained and used to suggest the mask fabrication performance based on P-D window analysis. In order to understand the influence of mask fabrication on patterns with various densities, the common P-D window is proposed. Using the P-D window, the optimized condition was achieved with a maximum process margin for the mask and wafer. In addition, the P-D window is used to quantify the scattering effect coming from the topographical mask and determine the effective 180° for the iso-focal condition.

Pattern dependence optical phase effect on alternating phase shift mask

A comprehensive study of alternating phase shifting mask (Alt-PSM) including mask making, 3-dimensional aerial image simulation, and wafer printing is reported in this paper. For the mask making, we found that the micro-loading effect will be greatly improved using the etching recipe with high Reactive Ion Etching (RIE) power and low Inductively Coupled Plasma (ICP) power. However, this recipe has side effects of Cr film damage and rough quartz side wall. Due to the 3-dimensional mask complex effect, the optimal phase difference is not simply π calculated using optical path difference but is varied with mask features. The optimal phase difference is 165° other than 180° for hole patterns, while it is 176° for line-and-space patterns. The micro-loading effect with variant 2-dimensional complexities is also studied in this paper.