Jay W. Strane

SOI FinFET versus bulk FinFET for 10nm and below

FinFETs may in principle be built on either bulk [1-3] or SOI [4-5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the other processes are as much the same as possible. Furthermore, we will discuss the challenges beyond the 10nm generation, where fundamental changes in materials may render the debate moot. Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice.

Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing

Addition of Pt to Ni silicide produces a robust [NixPt(1-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.

Ultrafast wafer alignment simulation based on thin film theory

The shrink of semiconductor fabrication ground rule continues to follow Moores law over the past years. However, at the 100 nm node, the fabrication cost starts to rise rapidly. This is mainly due tot he increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks, and more film layers makes the alignment signal more susceptible to process variations. Therefore in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection system based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Fin formation using graphoepitaxy DSA for FinFET device fabrication

A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.

Electrical Contacts to Metastable GexSi1−x Using Pd2Si as a Transport Layer

The transport of germanium through a co-deposited palladium-silicon layer on epitaxially grown Ge x Si 1−x on Si(100) was studied. The Ge concentration in the UHV-CVD grown Ge x Si 1−x film was x=.14 with a thickness of 155 nm. When the co-deposited layer is Pd rich with respect to Pd 2 Si, Ge was found to move through the Pd-Si layer and grow polycrystalline on the Ge x Si 1−x . Ge transport and Pd 2 Si(111) grain growth ceased simultaneously. No transport was found for Si rich Pd-Si layers. Electrical characterization showed the contacts were ohmic with a specific contact resistivity between 6–12 μωQ-cm 2 and an end resistance of.75 ω, resulting in a carrier concentration under the contact of 1.5×10 14 cm −2 . Hall effect measurements of the semiconductor gave n=5.77×10 14 cm −2 and μ=36.96 cm −2 /Vs. The sheet resistance of the contact layer was found to be 23.54 ω/square and the semiconductor was 237 ω/square.