Hiroyuki Akatsu

Study of the interfacial structure between Si (100) and thermally grown SiO2 using a ball‐and‐spoke model

Structural models of the a‐SiO2/(100)Si interface have been constructed using plastic balls and spokes to study the atomic scale structure of the thermally grown a‐SiO2/(100)Si interface. Various properties of the models such as distortion energy, composition, and interface undulation have been estimated on the basis of the models. The results of the simulation indicate that the energetically favorable interface is not flat but undulated with (111) facets or has a transition region with partially oxidized Si atoms. High‐resolution transmission electron microscopy images have also been simulated for the models.

Stoichiometry reversal in the growth of thin oxynitride films on Si(100) surfaces

Synchrotron‐based O 1s and N 1s photoabsorption spectroscopy, O 1s, N 1s, Si 2p, and valence‐band photoelectron spectroscopy (PES), and medium energy ion scattering (MEIS) have been used to determine the composition and thickness of oxynitride films grown in N2O on a Si(100) surface. Core‐level photoabsorption spectroscopy is shown to be a very sensitive probe capable of measuring surface coverages lower than 0.1 monolayers of N (6.5×1013 N atoms/cm2). Film composition was monitored as a function of growth to demonstrate the stoichiometry reversal from primarily N‐terminated surfaces in thin films to nearly pure SiO2 in films thicker than ∼20 A. A sample with a 60 A oxynitride film was depth profiled by etching in HF and was shown, via N 1s absorption spectroscopy, to have N segregation within 10 A above the Si/SiO2 interface. Core‐level PES and MEIS were used to study the growth mechanisms of oxynitrides on Si(100) and these data were used to create a schematic phase diagram showing three distinct region...

The structural models of the Si/SiO2 interface

In order to get a comprehensive understanding of a microscopic structure of the Si/SiO2 interfaces, various interface models constructed by using plastic balls and spokes have been characterized in terms of distortion energy and composition of the interface region in the models. The distortion energy has been represented by Keating-type potential. The composition has been simulated with our hypothetical atom probe measurements. The magnitude of the distortion energy at the interface depends on the orientation of crystalline Si and decreases in the order of (100), (110) and (111). The distortion energy at the (100)Si/SiO2 interface delineated by (111) facets is smaller than the one at the flat and abrupt interface. These results are in good agreement with TEM observations that the (111)Si/SiO2, interface is flat while the (100)Si/SiO2 interface is usually rough. A transition region which apparently seems to be stoichiometric SiO is identified by the hypothetical atom probe measurement between crystalline Si and SiO2 in the model of the (100)Si/SiO2 interface delineated by {111} facets.

HRTEM observation of the Si/SiO2 interface

Abstract Interfaces with crystalline Si (c-Si) and dry oxide grown over the c-Si have been observed using high resolution transmission electron microscopy (HRTEM). The lattice image of c-Si near the interface varies depending on the specimen thickness. For a very thin region of the specimen, the interface was observed to be very much roughened, and seemed to be abrupt (the so called interfacial layer was not observed between the c-Si and the amorphous SiO2 (a-SiO2)). On the contrary, the interface seemed to be flat and to consist of some steps of one or two monolayers high for the thick region. Furthermore, a lattice image with Si(220) periodicity has been observed at the interface. A possible structure for the Si/SiO2 interface derived from the observed interface image is that the roughened surface of the c-Si protrusions is directly connected to the SiO2 network with no interface layer between them. The observed flat interface of the thick region is a superposed image of the randomly distributed Si protrusions over the direction of the transmitted electron beam. In order to examine the postulated interface structure, a simulation of the lattice image has been performed. The results of the simulation indicate that the half-space image observed at the interface of the thick region can be attributed to the interface roughness, and the abrupt interface image observed for the thin region can be obtained by the same interface structure. Since a completely flat interface cannot provide such a specimen thickness dependence of the image, the (100)Si/SiO2 interface must be rough, and in our sample, the height of the roughness was about 4 monolayers.

Array pass transistor design in trench cell for Gbit DRAM and beyond

Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.

Structural model of amorphous silicon nitride

A continuous random network (CRN) model of amorphous Si 3 N 4 (a-Si 3 N 4 ) has been constructed using plastic balls and spokes. Radial distribution functions (RDFs) and structure factors of the model have been calculated and compared with experimental data. It has been found that a-Si 3 N 4 structure can be represented by a CRN model.

Technologies for scaling vertical transistor DRAM cells to 70 nm

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.

Ultrafast wafer alignment simulation based on thin film theory

The shrink of semiconductor fabrication ground rule continues to follow Moores law over the past years. However, at the 100 nm node, the fabrication cost starts to rise rapidly. This is mainly due tot he increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks, and more film layers makes the alignment signal more susceptible to process variations. Therefore in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection system based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N/sub 2/ implant prior to gate oxidation is important to reduce V/sub t/ roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V/sub t/ roll-off characteristics. Finally, the impact of halo implant on V/sub t/ variation in sub-0.2-/spl mu/m buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V/sub t/ variation in sub-0.2-/spl mu/m single workfunction gate pFET.

Stoichiometry reversal and depth-profiling in the growth of thin oxynitride films with N2O on Si(100) surfaces

Abstract Synchrotron base O 1s and N 1s photoabsorption spectroscopy have been used to determine the composition and thickness of oxynitride films grown in N 2 O on a Si(100) surface. Core-level photoabsorption spectroscopy is shown to be a very sensitive probe capable of measuring surface coverages lower than 0.1 monolayers of N (6.5×10 13 N atoms/cm 2 ). Film composiion was monitored as a function of growth to demonstrate the stoichiometry reversal from primarily N terminated surfaces in thin films to nearly pure SiO 2 in films thicker than ∼ 20 A. A sample with a 60 A oxynitride film was depth-profiled by etching in HF and was shown, via N 1s absorption spectroscopy, to have N segregation within 10 A above the Si/SiO 2 interface.