Sathish Veeraraghavan

Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners

Chucking of substrates with wafer shape and thickness variations results in elastic deformation that can cause significant in-plane distortions that lead to overlay errors in lithographic patterning. As feature sizes shrink, overlay errors due to the combination of wafer geometry and chucking become a larger fraction of the error budget and must be controlled. We use a finite element model and a lithographic correction postprocessing scheme to predict in-plane distortions that result from chucking wafers with shape variations. We then use the predictions of in-plane distortions at two different patterning steps to calculate the component of overlay error that arises from localized shape variations. Using the model, in-plane distortion and overlay errors due to chucking are examined for multiple wafers with different geometries. The results show that long spatial wavelength shape variations cause significant distortion, but can largely be mitigated through the use of simple first-order corrections that are applied in typical lithography scanners. In contrast, high-frequency spatial variations cause distortions that cannot be corrected and hence lead to meaningful overlay errors. The results provide fundamental insight into chucking-induced overlay errors and can serve as a basis for the development of higher order scanner correction schemes that explicitly account for the wafer geometry through high-density wafer shape measurements.

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Relationship between localized wafer shape changes induced by residual stress and overlay errors

The deposition of films with nonuniform residual stress can induce local changes in wafer shape and contribute to overlay errors with magnitudes that may be significant in advanced lithographic patterning processes. Understanding the fundamental relationship between residual stress, localized wafer shape changes, and overlay error is crucial for realizing new schemes to manage overlay errors, particularly at advanced nodes where feature sizes are smaller. In the present work, finite element modeling is used to quantitatively relate nonuniform residual stress in a deposited thin film to localized wafer shape changes and overlay errors. The results demonstrate that there is a strong correlation between localized shape variations induced by nonuniform residual stresses and noncorrectable overlay errors.

Electrostatic chucking for extreme ultraviolet lithography: Simulations and experiments

The purpose of this research is to assess the effectiveness of electrostatic chucks in reducing low-spatial frequency mask (or reticle) flatness variations and to validate finite element (FE) models of the chuck-mask interaction. The flatness of a sample extreme ultraviolet lithography reticle and an electrostatic pin chuck were measured using a Zygo interferometer. The measured flatness data were entered into the FE models, and electrostatic chucking was simulated by applying an area-weighted average pressure on the reticle. The shape of the mask when clamped by the electrostatic chuck was then predicted using the FE model. To validate these predictions, experiments were conducted in which the previously measured reticle was electrostatically clamped using the pin chuck. These experiments were conducted in a vacuum chamber to minimize the effects of humidity. Interferometric plots of the chucked reticle surface were obtained and compared with the FE predictions. It was found that the measured and predict...

Distortion of chucked extreme ultraviolet reticles from entrapped particles

Successful imaging of patterns with critical dimensions less than 45nm with extreme ultraviolet lithography (EUVL) requires stringent controls on all sources of image placement (IP) errors. Among the potential sources of IP error is the mechanical distortion of the patterned mask when mounted in the exposure tool. An EUVL reticle can exhibit both in-plane distortion and out-of-plane distortion due to the presence of debris lodged between the mask and the electrostatic chuck. Even particles with a compressed height as small as 100nm have the potential to consume a significant portion of the IP error budget. To alleviate this problem, a thorough understanding of the response of the reticle∕particle∕chuck system during electrostatic chucking is essential. This article describes experimental indentation testing to characterize relevant nanoscale material properties and the subsequent use of the data in finite element models that simulate the system response under typical chucking conditions.

Improvement of depth of focus control using wafer geometry

For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

Process induced Wafer Geometry impact on center and edge lithography performance for sub 2X nm nodes

The change to vertical NAND will make the process complexity increase in traditional steps for example high temperature furnace processing, film deposition using CVD, CMP to planarize the deposited film, film etching, wafer bevel and backside processing. With these significant changes in complexity, wafer topology will get worse and less stable. Our current methodology and technique to detect problems caused by wafer topology need a better metric to represent line performance. In this paper we will propose a new method using Patterned Wafer Geometry (PWG) tool to measure and detect wafer topology changes inline. This method will be compared to traditional methods like thickness measurement, defect scan, and probe data. PWG metrics were proven to predict yield or defect problem caused by wafer topology roll off, especially at the edge of the wafer. These metrics are capable of detecting intra-field topology change as well as wafer-to-wafer topology fluctuation. This new technique has the advantage of higher sampling rate and potential feed forward capability to stabilize inline performance.

Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.