Jean-Luc Everaert

Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi_x) and achieve ultralow contact resistivity (ρ_c) of (1.3 - 1.5) × 10^-9 Ω · cm² on Si:P. This PCAI + TiSi_x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi_x film, and moderate thermal budget (500°C-550°C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi_x-induced ρ_c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced ρ_c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low ρ_c is strongly correlated with the formation of interfacial TiSi_x crystallites between amorphous TiSi alloy and Si.

1 \times 10^{-9}

A method is described to determine the mobility of inversion charge carriers on Si substrates with SiO2 and HfO2 gate dielectrics. It is a completely contactless method combining corona charge and charge spreading metrology. [Patent Application Nos. EP 07118673 and U.S. 60940594.] It is shown that from such measurements mobility of inversion charge carriers can be calculated as a function of the effective electric field. The resulting mobility curves are comparable to those found in transistors.

Ohm-cm2

This paper reports ultralow contact resistivities (<inline-formula> <tex-math notation=LaTeX>

Contactless mobility measurements of inversion charge carriers on silicon substrates with SiO2 and HfO2 gate dielectrics

rho _{c})

TiSi(Ge) Contacts Formed at Low Temperature Achieving Around

</tex-math></inline-formula> achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; <inline-formula> <tex-math notation=LaTeX>

2 \,\, \times \,\, 10^{-{9}}~\Omega

rho _{c}

cm2 Contact Resistivities to p-SiGe

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Review of Silicon Nanowire Oxidation

sim 2.9times 10^{-9}~Omega cdot

The Application of an Ultrathin ALD HfSiON Cap Layer on SiON Dielectrics for Ni-FUSI CMOS Technology Targeting at Low-Power Applications

</tex-math></inline-formula>cm². The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; <inline-formula> <tex-math notation=LaTeX>

Lanthanum and Lanthanum Silicide Contacts on N-Type Silicon

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