C. Kerner

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

A novel silicide formation technique using milli-second anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6nm gate length reduction and more than 1 decade junction leakage imporvement.

8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS

We report low V<inf>t</inf> (V<inf>t,Lg=1µm</inf>=±0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>∼8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T<inf>inv</inf> (2) 220mV lower long channel pMOS V<inf>t</inf> (3) 21%/12% pMOS/nMOS drive current increase at I<inf>off</inf>=100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T<inf>inv</inf> of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

A novel bulk-Si based pMOSFET structure is presented featuring a high-mobility SiGe<inf>0.45</inf> channel and raised SiGe<inf>0.25</inf> source/drains. This device offers enhanced scalability with respect to standard pMOS devices, leading to 50% improved drive current. 30nm gate length devices show a high drive current of ∼580 µA/µm for I<inf>OFF</inf>=100nA/µm, DIBL=126mV/V, SS=80mV/dec, showing superior electro- statics without halo implants. Finally, the compatibility with additional strain-boosters is demonstrated.

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached at the same time. VT mismatch smaller than 3mV.µm is obtained for narrow (10nm) fins. Reduced speed sensitivity to gate pitch scaling and invertor delay reduced below 10 ps will be demonstrated.

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/mum Ioff), meeting the ITRS 45nm node requirement for low power CMOS

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack

We have demonstrated NMOS FinFET devices with a Vt of 0.33V through As implantation into TiN. The method allows for multiple Vt FinFET devices with Vts of 0.33V, 0.55V (NMOS) and -0.35V (PMOS) through just one As implantation step into lOnm TiN. The NMOS Vt can be further modulated by adjusting the As implantation dose. Further optimization of the cap, implantation and annealing conditions will be needed to keep the implantation damage away from the gate dielectric.