Jere A. M. Järvinen

A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.13- BiCMOS process is presented. The sensor interface consists of a front-end that converts the acceleration signal to voltage, two algorithmic ADCs, two frequency references, and a voltage, current, and temperature reference circuit. Die area and power dissipation are reduced by using time-multiplexed sampling and varying duty cycles down to 0.3%. The chip with a 0.51 active area draws 62 from a 1.8 V supply while sampling temperature at 100 Hz, and four proof masses, each at 1.04 kHz. With a 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 482 , 639 , and 662 , respectively.

2.4-GHz receiver for sensor applications

In this paper, a 3.4-mW direct-conversion receiver, operating at 2.4 GHz, is presented. The receiver includes merged low-noise amplifier and quadrature mixers, local oscillator buffers, and one analog baseband channel. The 0.13-/spl mu/m CMOS receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.

A Micropower Front End for Three-Axis Capacitive Microaccelerometers

This paper presents the measurement results of a micropower switched-capacitor front end that was designed for three-axis capacitive microaccelerometers. The designed front end can reduce the distorting effects of the electrostatic forces and can be used in single-ended and differential modes. The front end was realized with a 0.13-mum bipolar complimentary metal-oxide-semiconductor process. The silicon area of the front end is 0.30 mm2. The measurements show that the functionality of the front end follows the theory in both modes. Consuming 20 muA from a 1.8-V supply, it achieves noise densities of 424, 607, and 590 mug/radic(Hz) in the x-, y-, and z-directions, respectively, when each mass is sampled at 1 kHz in the differential mode.

A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm2 active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x, y and z directions is 460μg/radicHz, 550(μg/radicHz and 550μg/radicHz, respectively.

A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface

This paper describes a ratio-independent algorithmic ADC architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40 kS/s ADC with an active die area of 0.041 mm2 is implemented in a 0.13 mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4 muW power dissipation, the ADC achieves 80.2 dB SFDR and 63.3 dB SNDR.

A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC

This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion

A 1.2V Dual-Mode GSM/WCDMA - Modulator in 65nm CMOS

A dual-mode DeltaSigma ADC for a GSM/WCDMA direct-conversion receiver is implemented in a standard 65nm digital CMOS process and has a core area of 0.1mm2. With sampling frequencies of 48MHz and 96MHz, the ADC achieves peak SNDRs of 84dB and 49dB over the 100kHz GSM band and 1.92MHz WCDMA band, respectively. It draws 2.75mA in GSM mode and 3mA in WCDMA mode from a 1.2V supply

Direct-conversion receiver for ubiquitous communications

A direct-conversion receiver for a 2.4-GHz sensor network is described. The receiver is designed to operate in a Bluetooth system where slight changes are made in the radio parameters to meet the low power requirement. The receiver includes an LNA, downconversion mixers, a 90-degree phase shift circuit, analog filters, a 1-bit analog-to-digital converter, and a received signal strength indicator (RSSI). The receiver consumes 4.1 mA from a 1.2-V power supply and it achieves 43-dB voltage gain, 25-dB noise figure, -22-dBm IIP3, and +11-dBm IIP2.