Jesús Ruiz-Amaya

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.

A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time (DT) and continuous-time (CT) circuit techniques.

An optimization-based tool for the high-level synthesis of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators in the Matlab/Simulink environment

This work presents a Matlab toolbox for the automated high-level sizing of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/M) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known Matlab/Simulink platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic systems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/M using both discrete-time (DT) and continuous-time (CT) circuit techniques.

A comparative study of low-noise amplifiers for neural applications

This paper presents a comparative study of three low-noise amplifiers for neural recording applications. The topologies are thoroughly analysed in terms of area, power consumption and noise performance. Further, the theoretical results are confirmed by simulations of transistor-level implementations in a 0.13µm CMOS technology at 1.2V supply voltage.

Behavioral modeling of pipeline ADC building blocks

This paper presents accurate behavioral models for the basic building blocks of pipeline data converters with emphasis on the MDAC circuit. These models take into account major circuit-level non-idealities, including small- and large-signal effects, as well as the impact of switch-on resistance effects and thermal noise contributions. The behavioral models have been validated against transistor-level simulations under different scenarios, showing in all cases a worst-case deviation of 0.3 bit effective resolution. Copyright

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@1.2 V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.

Behavioral modeling simulation and high-level synthesis of pipeline A/D converters

The paper presents a MATLAB/sup /spl reg// toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK/sup /spl reg// C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speeds up system-level simulations while keeping high accuracy - verified with HSPICE - and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable CAD tool for the high-level design of broadband communication analog front-ends. As a case study, an embedded 0.13 /spl mu/m CMOS 12 bit resolution at 80 MS/s (Msamples/second) A/D interface for a PLC chipset is designed to show the capabilities of the presented tool.

A Low Noise Amplifier for Neural Spike Recording Interfaces.

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.