Ji-Myoung Lee

Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap

We developed titanium nitride (TiN) based nanoelectromechanical (NEM) switch with the smallest suspension air-gap thickness ever made to date by a “top-down” complementary metal-oxide semiconductor fabrication methods. Cantilever-type NEM switch with a 15-nm-thick suspension air gap and a 35-nm-thick TiN beam was successfully fabricated and characterized. The fabricated cantilever-type NEM switch showed an essentially zero off current, an abrupt switching with less than 3mV/decade, and an on/off current ratio exceeding 105 in air ambient. Also achieved was an endurance of over several hundreds of switching cycles under dc and ac biases in air ambient.

Polarization retention in Pb(Zr0.4Ti0.6)O3 capacitors with IrO2 top electrodes

The retention characteristics of Ir/IrO2/Pb(Zr0.4Ti0.6)O3(PZT)/Pt/IrO2 capacitors were investigated by measuring the switching and nonswitching polarizations, the switching current profiles, and the P–V hysteresis loops. The retention losses of Ir/IrO2/PZT/Pt/IrO2 capacitors were compared with those of the Pt/PZT/Pt capacitors, and a significant improvement of an opposite-state retention was observed. It was found that the growth and the relaxation behaviors of the internal field are quite similar for both capacitors, but that the polarization backswitching becomes significantly smaller for the PZT capacitors with the IrO2 top electrodes. The difference in polarization backswitching might originate from the nature of the ferroelectric/electrode interfaces, possibly suppressing the nucleation of opposite domains at the interfaces.

Mechanisms for retention loss in ferroelectric Pt/Pb(Zr0.4Ti0.6)O3/Pt capacitors

The switching current profiles of ferroelectric Pt/Pb(Zr0.4Ti0.6)O3/Pt capacitors were investigated after high-temperature baking to elucidate the mechanisms for retention loss. In the same-state retention, a decrease in the peak value of switching current and increase in the switching time were observed. These changes in the switching characteristics were attributed to the growth of an internal field. By comparing with the switching characteristics of a virgin capacitor and using the Merz equations, we estimated quantitatively the magnitude of the internal field. In the opposite-state retention, backswitching of polarization, triggered by the internal field, was found to be the main cause of the retention loss.

Polarization dynamics and retention loss in fatigued PbZr0.4Ti0.6O3 ferroelectric capacitors

Short-time retention loss behaviors were investigated for fatigued Pt/PbZr0.4Ti0.6O3/Pt capacitors. In the short-time regime of t<1 s, fatigued capacitors showed a significant loss in retained polarization, which could be well described by a power-law function. This behavior was interpreted in terms of a superposition of polarization relaxations with a relaxation time distribution. The effects of the pulse voltage on the relaxation time distribution suggested that the retention loss should be activated by a depolarization field. As the fatigue stress was applied, the retention loss became worse. This effect can be explained in terms of the increase of the depolarization field, possibly due to the growth of an interfacial passive layer.

Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger VTH shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.

Hydrogen-induced degradation in ferroelectric Bi3.25La0.75Ti3O12

Effects of forming gas annealing (FGA) were investigated on ferroelectric Bi3.25La0.75Ti3O12 (BLT) thin films fabricated by a chemical solution deposition. With the FGA up to 350 °C, the Pt/BLT/Pt capacitors showed good ferroelectric characteristics without significant degradation. As the FGA temperature was increased, a decomposition of the BLT powder sample was observed by using thermogravimetric analysis. By comparing the time-dependent weight loss of BLT with that of Bi4Ti3O12 during FGA, La doping was found to significantly impede the decomposition rate. The decomposition, especially in the (Bi2O2)2+ layers, was discussed as a hydrogen-induced degradation mechanism in the Bi-layered perovskite ferroelectrics.

Role of IrO2 Electrode in Reducing the Retention Loss of Ir/IrO2/Pb(Zr,Ti)O3/Ir Capacitors

Oxide electrodes are known to significantly improve reliability problems, such as fatigue and retention, in Pb(Zr, Ti)O3(PZT)-based ferroelectric capacitors. To understand the roles of the oxide electrodes on the opposite-state retention, we investigated the isotope tracer experiments and hysteresis measurements on Ir/IrO2/PZT/Ir and Ir/PZT/Ir capacitors before and after the retention tests. The depth profile of isotopic 18O in the Ir/IrO2/PZT/Ir capacitor, measured by the second ion mass spectroscopy, shows little changes in the 18O and 16O distributions at the IrO2/PZT interface. In addition, the hysteresis measurements showed that the internal field created by the retention tests should be nearly the same for both capacitors, indicating that the IrO2 layer should not play an important role in compensating the interface defect charges (possibly, the oxygen vacancies).

Mechanism of Charge Retention Loss in Ferroelectric Pt/Pb(Zr,Ti)O3/Pt Capacitors and Its Relation to Fatigue and Imprint

Charge retention loss was investigated for Pt/Pb(Zr0.4Ti0.6)O3/Pt capacitors in short- (t < 1 s) and long-time (t > 1 s) regimes. The short-time retention loss behaviors of fatigued capacitors were well described by a power-law function and analyzed in terms of a superposition of polarization relaxation with a distribution of relaxation time. We showed that depolarization field governs the retention loss in the short-time regime. Fatigue-induced defects, probably the interfacial passive layers, seemed to increase the depolarization field. In the long-time regime, the retention loss is shown to be related to the internal field developed parallel to the polarization direction. Particularly in “opposite-state” retention, the internal field caused polarization backswitching resulting in a severe degradation of retention characteristics. The internal field developed during retention was estimated by using Merz equations of polarization switching. Defects dynamics under electric field was discussed in conjunction with the recovery process of imprint.

Analysis of gate-induced drain leakage characteristics and threshold voltage modulation of plasma-doped FinFETs for low-power applications

FinFET devices were fabricated using plasma doping both at the source and drain extensions and in the channel region. In an effort to overcome dopant loss after the strip process, oxide buffer layers were deposited prior to plasma doping. Owing to the oxide buffer, 76% of the dopants were retained after the strip process and even after ashing, thereby keeping a high doping concentration of over 1 × 1020 atoms/cm3 on the surface of the Si fin. The gate-induced drain leakage (GIDL) current was decreased by 2 orders of magnitude due to the shallow and abrupt plasma doping, compared to the performance with an ion implantation method. The threshold voltage (V th) was shifted by 250 mV through plasma doping of the channel. The doping conformality was evaluated using electrical measurements and a newly-proposed method based on the GIDL data with various fin widths. The conformal doping profile with a smaller dopant loss provides a smaller GIDL current.

Sub-20nm Surrounding-Gate Bridge-Channel MOSFETs for Low Power and High Performance Applications

We compared electrical characteristics of TBCFET (Triple-Bridge-Channel MOSFET), MBCFET (Multi-Bridge-Channel MOSFET) and SBCFET (Single-Bridge-Channel MOSFET) with sub-20 nm gates. TBCFET is suitable for low-power application with 2.9 mA/um of on-state current and SNM (static noise margin) of 320 mV even at Vdd = 0.8V MBCFET and SBCFET, that are applicable to high-performance devices, show 4.17 mA/um and 2.16 mA/um of on-state currents at V^ = 1.0 V, respectively.