Jin-Hyung Park

Mask Pattern Recovery by Level Set Method based Inverse Inspection Technology (IIT) and its Application on Defect Auto Disposition

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Flowable CVD (Chemical Vapor Deposition) process having merits in terms of both superior gap-fill performance of SOD (Spin-on Dielectric) and process stability of CVD was introduced for the interlayer dielectric (ILD) in sub-20nm devices based on new concept and precursor. Remote plasma during low temperature deposition and ozone treatment was adopted to stabilize the film. We also developed a novel Flowable CVD process which does not oxidize Si or electrode, resulted in removal of Si3N4 stopper layer as an oxidation or diffusion barrier. After the application of Flowable CVD to 20nm DRAM ILD, we could reduce not only loading capacitance of Bit-line by 15% but also enhance comparable productivity. Through the successful development of sub-20nm DRAM ILD Gap-fill process, Flowable CVD was successful demonstrated as a promising candidate for mass production-worthy ILD in sub-20nm next generation devices.

Process monitoring system for instant defect detection and analysis in 65 nm node photomask fabrications

Defect is a killing factor in photomask fabrications. For 65nm node photomask fabrication, even smaller than 1 um particle can cause hard-to-repair defect. And it is not easy to find the defect source and solve it. For this reason, the process monitoring system that shows us current defect trend rapidly and effectively is highly required. At the same time, this system can be used for verifying the process stability and detecting unusual signals in process.

Phase defect printability analysis for chromeless Phase Lithography technology

Chromeless Phase Lithography (CPL) is one of the promising RETs for low K1 optical lithography. However, there are remained issues in CPL mask manufacturing, such as phase defect, which can be generated during quartz dry etching process. In CPL mask technology, the traditional defect printability specification is no longer adequate. This paper investigates to understand the tolerance of the CPL in view of phase defect specification. We studied to find out specifications for phase defect in CPL mask. Three-dimensional topography is used in the phase defect simulation. Based on the simulation results, programmed defect mask is made to evaluate phase defect printability by measuring aerial images with AIMS. Also the inspection sensitivity for quartz phase defect was evaluated with current inspection tool.

Development of mask-making process for CLM manufacturing technology

The extension of KrF lithography has become the major trend in semiconductor manufacturing due to the delay of ArF lithography. Therefore, various resolution enhancement techniques (RETS) are employed for sub 100nm node patterning. This paper introduces the 100 percent transmission PSM as a candidate for resolving the problems with previous approaches using a transparent phase-shift mask. CLM shows a high optical performance and relatively simple mask fabrication compare to other strong phase-shift mask. However, full-chip level CLM application is still under development due to the difficulty of mask manufacturing and lack of proper layout converting environment. In this paper, we covered mask-making process such as the quartz dry etch and defect engineering which are critical to CLM manufacturing. We made a test mask based on the basic CLM concept and evaluated its optical performance. Finally, we will show the feasibility of chrome-less mask manufacturing for real device application.