Jin-seok Kwak

Circuit and method for controlling on-die signal termination

Memory devices, systems and methods using selective on-die termination

Synchronous memory devices with synchronized latency control circuits and methods of operating same

Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same

Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof

Termination control circuit and its method

Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method

Semiconductor memory device capable of reading and writing data at the same time