Jing-Ye Juang

Assembly and reliability characterization of 3D chip stacking with 30μm pitch lead-free solder micro bump interconnection

Recently, the three-dimensional chip stacking technology with fine pitch and high input/output interconnects has emerged due to the requirements of multi-function and high performance in electronic devices. When the electronic packaging technology develops toward the miniaturization trend, the reliability of interconnect with fine pitch and high density solder bump interconnections will become a critical issue in advanced 3D chip stacking technology. In this study, assembly of chip-on-chip test vehicle with a micro bump pitch of 30 µm was demonstrated and the joint reliability was also evaluated. The Si chip/carrier used in this study had more than 3000 micro bumps with Sn2.5Ag solder material. Ni/Cu under bump metallurgy layer (UBM) was selected on both the top and bottom chip. 3D chip stacking was achieved by thermo-bonding and subsequently underfill dispensing for fine gap filling was also conducted with different kinds of underfills. The temperature cycling test was performed on the chip-on-chip stacking module over 1000 cycles. In addition, with the joint size becoming small, the current for each solder bump carried continues to increase. This leads high current flowing in each individual joint. Therefore, electromigration has become a major reliability issue in microelectronic devices. In this study, electromigration in SnAg solder micro bump with a pitch of 30 μm was investigated under 0.12A at 135°C. Electromigration characteristics of fine pitch micro bump was discussed with the microstructure evolution of micro bump during current stressing. The assembly of 3D stacking chip using two layers of chip with fine pitch and lead-free interconnects was achieved in this study. The results of reliability test showed that the reliability of fine pitch solder micro bump interconnections was acceptable under mechanical and electrical evaluations.

Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

In this study, we used a chip-on-chip test vehicle with 30μm pitch lead-free solder micro bump to study the electromigration reliability of solder micro bump interconnection used for 3D chip stacking. The structure of micro bump composed of Sn2.5Ag solder material with Cu/Ni under bump metallization (UBM) was selected. Two types of interconnection were chosen to evaluate the effect of the joint structure on electromigration behavior. The type I was the chip stacking sample with the IMC / Sn (5 um thick) / IMC joint structure, while the type II was the sample with fully transformed Ni3Sn4 intermetallic (IMC) joints made by the post-treatment of long time thermal aging. Electromigration test was performed on the four point Kelvin structure and daisy-chain structure under the current stressing of 104∼105 A/cm2 at an ambient temperature of 150°C. During the electromigration test, the resistance increase was in-situ monitored to determine the definite time to failure. The microstructure evolution was also examined at different stages of joint resistance increase. From the testing results, the rapid increase of joint resistance was found at the early stage under current stressing in the type I micro bump. After that, the joint resistance increase became slower. This mild increasing stage was much longer than the early stage. For the type II sample, however, the resistance increasing rate was quiet lower than that of the type I sample at the identical testing time. With a higher current density in the order of 105 A/cm2 in the micro joint, the effect of joule heating caused the damage happened in Al trace and Cu UBM while the residual Sn solder had been transformed to be Ni3Sn4 IMC totally and few voids were found around IMC by the microstructure observation. When applied a current density in the order of 104 A/cm2 on the micro joint, the residual Sn was also fully transformed to be IMC. However, the failure mode of the micro joint is not clear yet because the experiments are still on-going. The resistance variation is showing a steady state under such a condition of current stressing and so far no open failure happened.

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking

As the demands for portable electronic products increase, through-silicon-via (TSV)-based three-dimensional integrated-circuit (3-D IC) integration is becoming increasingly important. Micro-bump-bonded interconnection is one approach that has great potential to meet this requirement. In this paper, a 30-μm pitch chip-to-chip (C2C) interconnection with Cu/Ni/SnAg micro bumps was assembled using the gap-controllable thermal bonding method. The bonding parameters were evaluated by considering the variation in the contact resistance after bonding. The effects of the bonding time and temperature on the IMC thickness of the fabricated C2C interconnects are also investigated to determine the correlation between its thickness and reliability performance. The reliability of the C2C interconnects with the selected underfill was studied by performing a -55°C- 125°C temperature cycling test (TCT) for 2000 cycles and a 150°C high-temperature storage (HTS) test for 2000 h. The interfaces of the failed samples in the TCT and HTS tests are then inspected by scanning electron microscopy (SEM), which is utilized to obtain cross-sectional images. To validate the experimental results, finite-element (FE) analysis is also conducted to elucidate the interconnect reliability of the C2C interconnection. Results show that consistent bonding quality and stable contact resistance of the fine-pitch C2C interconnection with the micro bumps were achieved by giving the appropriate choice of the bonding parameters, and those bonded joints can thus serve as reliable interconnects for use in 3-D chip stacking.

Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Modeling and Experimental Validation

This paper aims at investigating the drop impact solder interconnect reliability of an advanced ultra-fine-pitch 3-D integrated circuit chip stacking packaging in accordance with JEDEC board-level test specification through finite-element (FE) simulation and experimental testing. To characterize the transient dynamic responses of the package, ANSYS/LS-DYNA incorporated with the Input-G method is applied. To well simulate the mechanical behaviors of the solder interconnects, a strain-rate-dependent elastoplastic Johnson-Cook constitutive model for the Sn3.5Ag solder is applied. In addition, an inverse calculation is carried out to identify the overall structural damping of the dynamic system. Furthermore, a JEDEC-compliant drop tester is used to conduct the drop test, where failure analysis is performed using an optical microscope. Moreover, a simplified Darveaux fatigue life prediction model is constructed based on the calculated strain energy densities at different JEDEC test conditions together with the corresponding drop test data. To demonstrate the validity of the developed fatigue life prediction model, a confirmatory experiment is performed. Finally, parametric FE study incorporated with experimental design is performed to seek a design guideline for enhanced solder interconnect reliability under drop impact. Both the experimental and simulation data reveal that underfill can greatly enhance the drop impact reliability of the solder interconnects. In addition, the cornered interconnects and even package in a one-component configuration would fail earlier than the central ones, with a cohesive fracture in the Sn3.5Ag solder rather than the intermetallic compound (IMC) and its interface. Besides, an increasing IMC thickness reduces the drop impact solder interconnect reliability while enhancing the thermal cycling one.

Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 um was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 um was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 um/10 um was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu6Sn5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150°C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.

Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30μm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed. Die-to-interposer test vehicle was adopted to develop the proposed adhesive bonding scheme. The micro joints of electroplating Cu/Sn solder micro bumps joined with electroplating Cu/Ni/Au micro bumps was selected as the joining structure. There were more than 3000 bumps designed in the test vehicle. Three types of wafer-level underfill material were evaluated and selected to be the suitable processing material. The optimized die-to-interposer boding profile by wafer-level underfill were developed and determined for the purpose of high throughput in this study. After assembly process by the developed adhesive bonding scheme, reliability characterization was conducted on the die-to-interposer modules. Pre-conditioning, temperature cycling test (TCT), thermal & humidity storage test (THST) and die shear test were selected to assess reliability performance of the die-to-interposer module assembled by the proposed adhesive bonding scheme. Under the optimized bonding profile, one-die assembly could be finished less than 20 seconds, which was comparable to the process time of thermocompression bonding only. Also, the wetting and joining abilities of the micro joints were as good as those bonded by thermocompression bonding with flux and no voids were found between dies. By such adhesive bonding scheme, processes of flux cleaning and underfill dispensing and curing were no longer necessary, which could apparently enhance the throughput of die stacking. Results of reliability tests revealed that no electrical-connectivity fail and delamination happened on those die-to-interposer modules with 30μm-pitch micro interconnects after TCT of 1000 cycles and THST of 1000 hours though die shear strength showed a slight degradation less than 20%. In this investigation, the developed high throughput adhesive bonding scheme displayed the high potential that could be suitable and applicable for fine pitch 3D integration and high volume manufacturing requirements.

Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30μm-pitch solder micro bump interconnection

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

The development of high through-put micro-bump-bonded process with non-conductive paste (NCP)

In this study, various micro-bump-bonded structures with TCB + NCP processes were evaluated and developed. A commercial available snap-cure NCP material was applied for the joining processes study. Three types of micro bumps, Cu/Ni/Sn2.5Ag, Cu/Sn2.5Ag and Cu/Ni/Au- were fabricated and bonded to achieve joint structures of Cu/Ni/Sn2.5Ag/Ni/Cu, Cu/Ni/Sn2.5Ag/Au/Ni/Cu and Cu/Sn2.5Ag/Au/Ni/Cu. Moreover, the filler trapped and void issues which associated with the TCB+NCP process were also investigated. After the evaluation, the reliability test such as moisture sensitivity test level 3 (MSL 3), temperature cycling test (TCT) and high temperature Storage (HTS) were conducted to the bonded samples. Hereafter, the failure modes with the mentioned issues were analyzed and discussed. Based on the experimental and reliability results, the optimized TCB + NCP processes with various micro-bump-bonded structures can be established. The joints electrical and reliability performance associated with the failure mode were investigated and analyzed. Finally, the characteristics of each joint connection were defined.