Su-Mei Chen

Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure

In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.

Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 um was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 um was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 um/10 um was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu6Sn5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150°C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.

Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30μm-pitch solder micro bump interconnection

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

Low temperature bonding of 30um pitch micro bump interconnection for 3D IC stacking using non-conductive adhesive

For evaluating the feasibility of adhesive bonding by NCF (non-conductive film) in micro bump joints, three types of micro joints were adopted in this study. The structure of the type I micro joints was Cu/Ni/Au while that of the type II micro joints was Cu/Ni/Au micro bump joined with Cu/Sn solder micro bump. Both the type I and type II micro joint were bonded by using NCF. The structure of the type III micro joints were the same, but the type III micro joints were produced by eutectic bonding. For the type III micro joints, the micro gap between chips was wrapped by a capillary underfill. The bonding results revealed that the contact resistance of the NCF joints was in the range of 100 Qm ∼ 400 Qm which was higher than that of eutectic joints. Electrical continuity of micro bump interconnection was monitored by measuring the contact resistance of four-point Kelvin structure and daisy chain during reliability test. Thermal cycling test and thermal humidity storage test were conducted to evaluate the reliability performance of these three types of micro interconnections. The reliability test displayed that the reliability performance of eutectic joints was better than that of the NCF joints. The study showed that NCF joints have great potential to be applied in low temperature bonding of fine pitch 3D IC stacking.

A novel 3D IC assembly process for ultra-thin chip stacking

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30μm or less than 30μm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

Bonding and reliability assessment of 30 μm pitch solder micro bump interconnection with various UBM structure for 3D chip stacking

With the increased demand of multifunction in electronic device, downscaling of interconnection pitch presents an important role for the next generation electronics with high performance, small form factor, low cost and heterogeneous integration. In the current types of interconnects, solder micro bumps have received much attention due to its low cost of material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the solder micro bump joints with different kinds of UBM material will present varied reliability performances. However, which structure of solder micro bump joint shows the better reliability properties is not concluded yet until now. In this study, three-dimensional (3D) chip stacking using 30μm pitch interconnects with lead-free solder bumps and two types of UBM material is described. The reliability of solder micro bump interconnection with varied UBM material is also discussed. Assembly of the chip-on-chip test vehicle with a micro bumps diameter of 18 μm and a pitch of 30 μm was conducted. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. Two kinds of UBM layer on Si chip were selected in this study: one was single copper layer with a thickness of 8 μm and the other was Cu/Ni layer with a total thickness of 8 μm. The UBM was electro-plated on Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. During bonding process, the micro joints were formed at a peak temperature of 250 °C and the microgaps between chips were then filled by a capillary underfill cured at 150°C for 30 min. In this study, we evaluate the effect of fluxless bonding on the joining ability of solder micro bumps. The influence of underfill on the reliability of solder micro bump interconnections was estimated also. Subsequently, the chip-stacking modules were inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of micro joints including bonding accuracy, formation of interconnections and the percentage of voids within the underfill. Afterwards, the moisture sensitivity level 3 pre-conditioning test and temperature cycle test for 1000 cycles were performed to evaluate the reliability of solder micro bump interconnects. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation.

Reliability test for integrated Glass interposer

In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

The electrical characterizations of glass interposer for integrated reliability test

In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

Effects of bump height and UBM structure on the reliability performance of 60µm-pitch solder micro bump interconections

Recently, three dimensional integration circuits technology has received much attention since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are required. In the current types of interconnects, solder micro bumps have been widely adopted. For fine pitch solder micro bump joints, selections of bump height and UBM structure are the important issues that would show the significant effects on the reliability performances of solder micro bump interconnection. In this study, effects of bump height and UBM structure on the reliability properties of lead-free solder micro interconnections with a pitch of 60μm were discussed. The chip-to-chip test vehicle having more than 4290 solder micro bump interconnections with a bump pitch of 60μm was used in this study. To evaluate the effects of bump height and UBM structure on the reliability performance of micro joints, two groups of solder joint were made. The first group of micro joints had a total bump height of 29μm. In this group, Cu/Sn/Cu joint with a thickness of 7μm/15μm/7um, Cu/Sn/Ni/Cu joint having a thickness of 7μm/15μm/2μm/5μm and Cu/Ni/Sn/Ni/Cu joint with a thickness of 5μm/2μm/15μm/2um/5μm were selected. The second group of micro joints had a total bump height of 24μm. In this group, Cu/Sn/Cu joint having a thickness of 7μm/10μm/7um, Cu/Sn/Ni/Cu joint with a thickness of 7μm/10μm/2μm/5μm and Cu/Ni/Sn/Ni/Cu joint having a thickness of 5μm/2μm/10μm/2um/5μm were chosen. We used the fluxless thermocompression bonding process to form these two groups of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of bump height and UBM structure on the reliability properties of those two groups of solder micro bump interconnections.