Thomas-Michael Winkel

Extraction of /spl epsiv//sub r/(f) and tan/spl delta/(f) for printed circuit board insulators up to 30 GHz using the short-pulse propagation technique

In this paper, the self-consistent, frequency-dependent dielectric constant epsivr(f) and dielectric loss tandelta(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique

Determination of the propagation constant of coupled lines on chips based on high frequency measurements

A new method has been developed to determine the propagation constant of symmetrical coupled lossy lines. The results are based on high frequency measurements of the scattering parameters of only two coupled two line systems of different lengths. The mathematical derivation of the method is be given. The proposed method is related to an eigenvalue calculation. Results obtained from measurements are presented and discussed. A comparison between the measured and calculated results is given and shows excellent agreement.

First- and second-level packaging of the z990 processor cage

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

First- and second-level packaging for the IBM eServer z900

This paper describes the system packaging of the processor cage for the IBM eServer z900. This server contains the worlds most complex multichip module (MCM), with a wiring length of 1 km and a maximum power of 1300 W on a glass-ceramic substrate. The z900 MCM contains 35 chips comprising the heart of the central electronic complex (CEC) of this server. This MCM was implemented using two different glass-ceramic technologies: one an MCM-D technology (using thin film and glass-ceramic) and the other a pure MCM-C technology (using glass-ceramic) with more aggressive wiring ground rules. In this paper we compare these two technologies and describe their impact on the MCM electrical design. Similarly, two different board technologies for the housing of the CEC are discussed, and the impact of their electrical properties on the system design is described. The high-frequency requirements of this design due to operating frequencies of 918 MHz for on-chip and 459 MHz for off-chip interconnects make a comprehensive design methodology and post-routing electrical verification necessary. The design methodology, including the wiring strategy needed for its success, is described in detail in the paper.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

An accurate determination of the characteristic impedance matrix of coupled symmetrical lines on chips based on high frequency S-parameter measurements

A new method has been developed to determine the characteristic impedance matrix of a symmetric coupled lossy two line system on chips. The presented results are based on high frequency measurements of the scattering parameters. A comparison between the measured and analytical calculated results is given and shows excellent agreement.A new method has been developed to determine the characteristic impedance matrix of a symmetric coupled lossy two line system on chips. The presented results are based on high frequency measurements of the scattering parameters. A comparison between the measured and analytical calculated results is given and shows excellent agreement.

Crosstalk analysis in high density connector via pin fields for digital backplane applications using a 12-port vector network analyzer

In this paper the authors present results from the crosstalk analysis of a high density single ended connector and its associated card via array obtained with 12-port vector network analyzer (VNA) measurements in the bandwidth from 10 MHz up to 20 GHz. The device under test used for this paper is typical for a high end mainframe processor node to node link scenario consisting of daughter cards plugged into a backplane card by using a multipin connector. In previous studies the authors have shown that mainly the connector via pin field is impacting the electrical link performance. Here, the measurements have shown that the via pin field constitutes a complex crosstalk problem depending on the orientation and the distance between victim and aggressor via, the common coupled via lengths, and the local power/ground environment.

High-speed interconnect and packaging design of the IBM System z9 processor cage

This paper describes the system packaging and technologies of the IBM System z9TM enterprise-class server. The central electronic complex of the system consists of four nodes, each housing a multichip module (MCM) with 16 chips consuming up to 1,200 W. The z9TM server doubles the multiprocessor performance of the System z990 by increasing the central processing unit (CPU) configuration and using an internally developed elastic interface to increase interconnect speed on all high-speed buses. In contrast to all previous zSeries® designs, which were running at half of the processor speed, the packaging interconnects on the multichip module run at the same speed as the processor (1.72 GHz). High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.

Analysis and Mitigation of Parasitic Mode Conversion for Microstrip to Stripline Transitions

In this letter, the parasitic mode conversion that occurs at microstrip to stripline transitions is analyzed through electromagnetic simulations and an equivalent circuit including the parallel-plate impedance. It is shown that the excitation of plate modes can significantly impact transmission and crosstalk parameters, and that mitigation of mode conversion by the utilization of return vias is feasible.

Packaging design challenges of the IBM system z10 enterprise class server

This paper describes the system packaging and technologies of the IBM System z10™ high-end Enterprise Class server. This machine exceeds the multiprocessor performance of the previous system by 50%. A new generation of the IBM Elastic Interface was developed in order to maintain the increased interconnect signal speed of up to 2.93 Gb/s. Power control and power delivery to the multicore processors were a special challenge for the server packaging because of the high currents and the high number of voltage domains.