Roland Frech

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end server processor

The next processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.

Frequency dependencies of power noise

In this paper, frequency dependencies of delta-I noise caused by variations of the on-chip switching activity have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching frequency and the noise source waveform have been varied in case of a single delta-I step. For repeated delta-I steps the power noise dependencies on the repetition frequency, the duty cycle and the damping of the resonant loop have been analyzed. Simulations using switching current sources for on-chip switching have been confirmed by simulations with switching resistors plus de voltage source. Mid-frequency noise simulations using SPEED2000 and noise voltage measurements yield the same results within 6% for the first and second voltage droops and overshoots, if the real resistance of power/ground vias and module pins are included in the simulation.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%.

Crosstalk analysis in high density connector via pin fields for digital backplane applications using a 12-port vector network analyzer

In this paper the authors present results from the crosstalk analysis of a high density single ended connector and its associated card via array obtained with 12-port vector network analyzer (VNA) measurements in the bandwidth from 10 MHz up to 20 GHz. The device under test used for this paper is typical for a high end mainframe processor node to node link scenario consisting of daughter cards plugged into a backplane card by using a multipin connector. In previous studies the authors have shown that mainly the connector via pin field is impacting the electrical link performance. Here, the measurements have shown that the via pin field constitutes a complex crosstalk problem depending on the orientation and the distance between victim and aggressor via, the common coupled via lengths, and the local power/ground environment.

Simulations of frequency dependencies of delta-I noise

In this paper frequency dependencies of delta-I noise caused by variations in on-chip switching activity has been studied for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching cycle has been varied in case of a single delta-I step and the effect of repeated delta-I steps and variations of the delta-I repetition frequency and the duty factor have been analyzed.

Impact of Broken High Frequency Signal Return Path on Signal Integrity

Special test vehicles with and without broken high frequency signal return paths were built in order to measure their impact on signal integrity. Design guidelines for the transition between different packaging levels are derived and discussed

Issues and challenges of Gbps backplane connector characterization

Current high-end inter-processor links run hundreds of signals at Gigabit per second data rates over one or two connectors and tens of inches of backplane. Suitable connectors have to fulfil tight crosstalk, reflection, and attenuation specifications. Accurate connector measurements and models are critical to the successful design of the whole link. However, due to high pin count and interdependencies with the backplane environment connector characterization is still a challenging task. Here, a 50 Ohm single-ended, pin-in-paste prototype connector system from ERNI is analyzed in detail. Comprehensive 3D full-wave EM simulations were done and compared to measurements. Several de-embedding techniques are presented to extract the connector response from the test environment. It will be shown that the connector footprint on the backplane has a major impact on the overall electrical performance.

Effects of partially broken HF signal return on different packaging levels

Electro magnetic field effects for broken high frequency (HF) signal returns are analysed for discontinuities in different packaging levels. Board connectors with a huge signal count and high speed signals as well as typical multi chip module structures are analysed using 3D field calculations. Resulting coupling effects were calculated and also verified with time domain measurements. The results are discussed with respect to the impact on signal integrity.