John Clayton Foster

Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi

CMOS devices down to 50 nm gate length were fabricated with NiSi salicide for the first time. Edge effects of Ni-polycide formation, enhanced by a recessed spacer, results in gate Rs roll-off with poly line width. Ultra low /spl sim/2 /spl Omega///spl square/ gate Rs is achieved for 50 nm line width with low junction leakage. Source/drain series resistance is significantly reduced and, consequently, drive current is improved with NiSi. Ring oscillator speed measurements showed significant improvement in gate delay with NiSi, especially for the ring oscillators made with large gate width devices.