Paul L. King

Artifacts in AES microanalysis for semiconductor applications

Auger electron spectroscopy analyses of submicron features on semiconductor surfaces are routinely accompanied by analytical artifacts such as sample degradation and background contributions arising from electron beam scattering. Submicron analyses are commonly carried out at electron beam densities in excess of 1 A cm -2 and are especially damaging to silicon oxides. The evolution of oxide reduction is observed both as a loss of oxygen versus beam exposure and in a complementary growth of Si LVV and Si KLL elemental peaks. The O KLL signal intensity from a 1 μm 2 area of thermally grown oxide is found to decrease by 22% after exposure to a rastered 20 kV/10 nA beam for 10 min. Another aspect of submicron analysis is the contribution to survey spectra that originates when surrounding material is excited by backscattered electrons. Background contributions may dominate AES spectra even when the sample is flat and the probing beam is smaller than the feature of interest. Tungsten damascene contacts provide a useful platform for investigating this phenomenon in the absence of topography. Spectra have been collected from tungsten contacts of various sizes and the target and background contributions quantified. When a 0.25 μm diameter tungsten contact is probed with a narrow 20 kV beam, the W MNN signal intensity is determined to be only 70% of that emitted from a large tungsten structure. Target signal reduction coincides with increased signal contributions from the surrounding oxide.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.