Eric N. Paton

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

Band offset induced threshold variation in strained-Si nMOSFETs

Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth.

Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi

CMOS devices down to 50 nm gate length were fabricated with NiSi salicide for the first time. Edge effects of Ni-polycide formation, enhanced by a recessed spacer, results in gate Rs roll-off with poly line width. Ultra low /spl sim/2 /spl Omega///spl square/ gate Rs is achieved for 50 nm line width with low junction leakage. Source/drain series resistance is significantly reduced and, consequently, drive current is improved with NiSi. Ring oscillator speed measurements showed significant improvement in gate delay with NiSi, especially for the ring oscillators made with large gate width devices.

High performance 25 nm FDSOI devices with extremely thin silicon channel

We demonstrate 25 nm mid-gap metal gate fully-depleted silicon on insulator (FDSOI) devices with the highest reported drive current for a single-gate PMOS device (I/sub on/=789 /spl mu/A//spl mu/m and I/sub off/=27 nA//spl mu/m for V/sub gs/-V/sub t/=1.25 V). We observe electron and hole mobility degradation for very thin channels (/spl sim/7 nm). Devices show good hot carrier and gate dielectric reliability.

Optimizing the target-to-wafer spacing for highly uniform PVD films

This research examines the optimum spacing between the Physical Vapor Deposition (PVD) target and the wafer substrate, at various stages in the erosion life of the target. As the target erodes, the surface becomes uneven with ring shaped grooves. This effects the radial distribution of material flux onto the wafer, and requires the wafer to be moved further from the target. The optimal target to wafer spacing is plotted against target lifetime for different types of chamber configurations and target materials. Target materials are Ti, TiN, and Al, and chamber configurations are standard Magnetron PVD, Collimated PVD, and Ionized Metal Plasma (IMP) PVD. TiN chambers with Dura TTN magnets show predictable behavior during the life of the target, while Type A magnets and all other chamber configurations show almost now drift in the optimum spacing. Thus, it was decided only Dura TTN (TiN) chambers required spacing compensation. Rate-of- change constants for TiN chambers were input into software provided by Applied Materials, to dynamically adjust the spacing as the target erodes. Thickness uniformity of less than 1% was maintained throughout the targets 1600 KWHrs life.