John T. Yue

Stress Induced Voids in Aluminum Interconnects During IC Processing

Voids in the aluminum metallization of integrated circuits can be created under certain device fabrication conditions. The formation and characteristics of these defects have been studied in detail. It is found that the density and size of the metal voids have a strong functional dependence on the compressive stress of the passivation film. The study shows that metal voids occur in a wide class of Al systems, including E-beam evaporated pure Al, and those sputtered with Si and Si-Cu. Physical characterization, quantification of stress relationships, grain size dependence, temperature stability, and the effect of the metal voids on electromigration are discussed.

Simulations of CMOS circuit degradation due to hot-carrier effects

By comparing long-term ring-oscillator hot-carrier degradation data and simulation results the authors show that a public-domain circuit simulator, BERT (Berkeley Reliability Tools), can predict CMOS digital circuit speed degradation from transistor DC stress data. Large initial PMOSFET drain current enhancement can result in initial frequency enhancement followed by an initial fast degradation due to the zero crossing effect. The relationship between circuit lifetime and transistor DC stress is examined.<<ETX>>

Drain-avalanche induced hole injection and generation of interface traps in thin oxide MOS devices

Drain-avalanche-induced hot hole injection in thin oxide MOS devices, used in flash-type EEPROM memory cells, is discussed. A significant amount of acceptor-like interface traps are generated by the injected hot holes, spreading into the channel region. These generated interface traps dramatically alter the channel hot carrier characteristics of the device. This can adversely affect the programmability of a flash memory cell and can cause early window closure. >

A method to project hot carrier induced punch through voltage reduction for deep submicron LDD PMOS FETs at room and elevated temperatures

The hot-electron-induced punchthrough (HEIP) voltage (V/sub pt/) characterization technique, which can be used for half- and sub-half-micron lightly doped drain (LDD) PMOS reliability characterization, was established. It was found that, unlike other hot carrier effects, the punchthrough due to HEIP at room temperature or the temperature effects plus HEIP at higher temperatures is the most significant limitation for deep submicron LDD PMOSFETs. The high-temperature effects of V/sub pt/ were also quantified at 25 degrees C, 80 degrees C and 125 degrees C ambient temperatures. The oxide quality dependence of the HEIP was also studied.<<ETX>>

Hot-carrier-induced off-state current leakage in submicrometer PMOSFET devices

Hot-carrier-induced off-state leakage (HCIOL) currents were successfully used as a new monitor in characterizing device reliability. HCIOL current increases drastically with reducing channel length, but the stress bias only affects the onset time of HCIOL current. For buried-channel PMOSFETs, only the HCIOL currents at the reverse measurement configuration were dominant. However, in surface-channel devices, HCIOL currents at both forward and reverse configurations became important. An empirical HCIOL current model was developed to quantify device lifetime as a function of channel length and stress voltage. Estimated lifetime results indicated that HCIOL current will impose a major limit on device reliability especially for deep-submicrometer technology and low power applications.<<ETX>>

A comparison of inverter-type circuit lifetime and quasi-static analysis of NMOSFET lifetime

Performance degradation of inverter-type circuit due to hot carrier injection is investigated. Frequency degradation of the ring oscillators was used as a monitor of the circuit performance for very short gate delay transients. A quasi-static approach was used to correlate the circuit performance with various parameter degradations of discrete NMOSFETs. It is shown that the degradation behavior of the circuit with time is quite different from that of a discrete device. The quasi-static calculations underestimate the degradation in CMOS inverter propagation delay and overestimate the predicted lifetime. The results indicate that created electron traps may be the cause for enhanced degradation.<<ETX>>

A via failure mode in electromigration of multilevel interconnect

Via electromigration (EM) performance of (Al-1% Si-0.5% Cu)/(Ti/TiN/Al-1% Si-0.5% Cu) metallization systems has been evaluated for vias with sizes ranging from 1 mu m to 2 mu m. The electrical open failure mode for vias was observed during EM test at high temperatures and with different current densities. The activation energy and current exponent were obtained, suggesting surface and lattice diffusion as the probable failure mechanisms. A novel observation from this study was the self-healing of failed vias when the failed chains were stored at room or high temperatures. A model for the failure mechanism is proposed.<<ETX>>

Impact of Ceramic Packaging Anneal on the Reliability of Al Interconnects

Experimental results show conclusive evidence that stress induced metal voids and Si nodules (both of which originate during wafer processing) grow significantly after Ceramic Packaging (CDIP) glass sealing anneal. Furthermore, the growth of a metal void is almost always accompanied by Si precipitation in its immediate neighborhood. The combination of a metal void and an adjacent silicon nodule was observed to significantly reduce the net metal line cross-sectional area and is highly undesirable for interconnect reliability. In this paper the above phenomenon is fully explained and the effects of COIP anneal temperature profiles are examined.

A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient

We developed a quick experimental technique for evaluating the cumulative plasma charging current density with MOSFETs. A one second stress at 9 volts for gate oxide thickness of 100A is sufficient to force the Fowler-Nordheim tunneling condition to reveal the plasma-induced oxide damages to the MOSFET, then the oxide damages can be easily characterized by I-V meansurement. In addition, we suggested an experimental method in estimating the limitation and reliability of the protection diode in the plasma ambient under various plasma charging conditions.

An investigation of hot carrier effects in submicron CMOS integrated circuits

Abstract The Static (DC) and Dynamic (AC) Hot Carrier effects on discrete transistors and ring oscillator test structures were reviewed. The relationship between degradations of integrated circuit AC performance and individual device under the DC stress condition was further explained by including 1) effects of hot carrier degradation of PMOS transistors in AC hot carrier modeling; 2) trappy and normal oxide characteristics of PMOS transistors. The models were applied to simulate the CMOS integrated circuit degradation due to hot carrier effects successfully. The simulated AC circuit degradation were verified by long term experimental results.