Jon Guerber

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-μm CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 μ W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm

The early reset merged capacitor switching algorithm (EMCS) is proposed as an energy reducing switching technique for a binary weighted, capacitive successive approximation (SAR) analog to digital converter (ADC). The method uses the merged capacitor switching (MCS) architecture and optimizes the use of the VCM level during the SAR conversion. This algorithm can reduce switching power by over 12% with no additional DAC driver activity when compared to the MCS scheme. The MCS and EMCS approaches are analyzed mathematically and the EMCS energy consumption is shown to be lower than or equal to that of the MCS technique for every digital code. Static linearity improvements for this structure are also shown with the integral non-linearity (INL) reducing by a factor of two due to the utilization of the MCS three level DAC. The EMCS implementation methodology is also described.

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC nonlinearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and nonideal traditional multistage ADC structures.

A 10b Ternary SAR ADC with decision time quantization based redundancy

The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.

Blind background calibration of harmonic distortion based on selective sampling

This paper proposes a blind calibration algorithm for suppressing harmonic distortion in analog to digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the harmonic distortion coefficients. The algorithm can be operated in both foreground and background modes to remove even and odd harmonics simultaneously. The algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is harmonic distortion limited. Built in 0.13μm, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB.

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling

This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 μm CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB.

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters

This paper presents detection and correction methods for single event effects in analog to digital converters. Multi-path ADC based detection method is proposed for single event effects and bit error rate. Two correction schemes are proposed for single event effects based on multi-path ADC structure. Two-path ADC based detection scheme with skip and fill algorithm based correction scheme. Three-path ADC based detection scheme with majority voting based correction scheme. Advantages and limitations of both the methods are presented with simulation results. In particular, the three-path ADC can detect and correct for single event effects independent of repetition rate, magnitude of single event effects and the choice of data converter architecture. In three path ADC technique, the accuracy degradation is less than 1.7 dB or 0.28 bit for the Nyquist bandwidth for single event effects. Bit-Error Rate (BER) is effectively squared for three-path ADC as compared to a conventional ADC.

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits

This paper demonstrates Class-A+ amplifier as an alternative to Class-A amplifier for discrete-time signal processing circuits. Class-A+ amplifier uses cross-coupled latches during the amplification phase at the output to improve settling accuracy compared to Class-A amplifier. The positive feedback latch is reset to fixed bias voltages of the Class-A output stage during the reset-phase. This dynamic compensation technique for realizing stable amplifier enables power and area savings with improved settling accuracy and THD performance. Simulation results show 30% reduction in overall power consumption, 50% reduction in the size of output stage and 10 dB improvement in settling accuracy compared to conventional Class-A amplifier with similar worst case settling time.

Correlated jitter sampling for jitter cancellation in pipelined TDC

In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1st time quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1TLSB in reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC.

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters

This paper analyzes the effect of bit error rate on ADC performance and presents triple modular redundancy method for data converters. A comparison among different analog to digital converters (including successive approximation register, algorithmic/cyclic, and pipeline ADC architectures) are discussed. It is shown that a multi-path architecture provides the ability to measure and correct bit errors, squaring the bit error performance without additional analog area or power. We provide a comparative study of bit error rate among the different architectures and an error power calculation method that may be applied to further variations on these architectures, without time-consuming transient simulations.