Allen Waters

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-μm CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 μ W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.

A 10b Ternary SAR ADC with decision time quantization based redundancy

The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.

Analysis of metastability errors in asynchronous SAR ADCs

Previous work has provided detailed analysis of metastability errors and SMR for synchronous SAR ADC. This work extends the analysis to the Asynchronous SAR (ASAR), for which metastability errors are more difficult to understand and quantify. Since the relationship between SMR and conversion time cannot be reduced to a closed-form solution, a framework is instead provided for using numerical simulation results to determine the necessary conversion time such that metastability errors will not limit resolution. Two main contributions are made using this framework: first, the designer may determine the maximum effective sample rate for the ADC (and therefore the speed benefit over the synchronous SAR); second, it is shown that proximity detectors are not effective solutions to improving metastability performance.

LSB-first SAR ADC with bit-repeating for reduced energy consumption

Least-significant bit first quantization (LSBFQ) is presented as an energy-efficient method for analog-to-digital conversion (ADC) when input signal activity is low. LSBFQ has been shown to conserve switching energy and comparator bitcycles, but certain code transitions will force unnecessarily large steps in the DAC output code and degrade the performance. A novel bit-repeating LSBFQ algorithm is proposed which prevents these undesirable code steps. It is shown that the proposed algorithm saves switching energy over previously published LSBFQ in all cases. For low signal activity (the intended target application for LSBFQ) the proposed LSBFQ method even outperforms merged capacitor switching (MCS), which is the most energy-efficient of the traditional MSB-first SAR methods.

Stochastic approximation register ADC

In this paper a stochastic approximation register ADC is proposed. The ADC is capable of achieving an ENOB of up to 10 bits. The ADC is composed of a variable noise engine, a bank of comparators with Gaussian offset noise, and a DAC. The ADC is simulated to achieve over 10 ENOB across various non-idealities using a comparator bank containing 1200 digital-cell based comparators with an input referred offset standard deviation of 12 mV.

A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing

This paper describes a comparator capable of detecting mV-range input voltage signals reliably using sub-nW power consumption. The comparator uses a current-mirror-based positive feedback and hysteresis to generate the mV-range threshold. It has three new ideas: (1) to use the input signal to bias the current mirror, which only activates the current mirror when the input signal reaches a detectable threshold; (2) to achieve dynamically controllable detectable threshold by using control signals to adjust the mirror transistor sizes; and (3) to use negative feedback to compensate the process-voltage-temperature variation. Preliminary SPICE simulation results using state-of-the-art 9HP (BiCMOS) have shown that the proposed hysteresis-based comparator can achieve the following performance metrics: 1) Very low comparator threshold (in the range of mV); furthermore, these threshold voltages can be programmable at run-time from a few to tens of mV. 2) Steep equivalent subthreshold slope in the range of sub-mV/decade. 3) Ultra-low leakage power (in the sub-nW range for a 0.1mV input voltage) and switching energy (in the nW range). The proposed hysteresis-based comparator only requires one standard logic supply source (working over 1V to 0.5V). Furthermore, initial simulations have shown that this comparator threshold is reliable over the process and voltage (PV) variations, and linearly proportional to temperature (T) variation.

Analysis and performance trade-offs of linearity calibration for stochastic ADCs

Stochastic flash analog-to-digital converters (ADCs) have been proposed as a solution to the scalability problems encountered by a standard flash ADC. Instead of generating comparator references with a well-matched resistor ladder, it generates randomly distributed thresholds using either the comparator offsets or a separate noise-generating circuit. This allows all devices to be minimum size without matching problems; consequently the stochastic ADC becomes an attractive solution for a synthesizable ADC design. This work achieves two goals: first, it derives the relationship between the number of comparator decisions and effective resolution of a stochastic ADC with an arbitrary probability distribution function (PDF) of comparator thresholds. Second, this work identifies the conditions under which linearity calibration will improve performance. Monte-Carlo simulations demonstrate that for high signal amplitude or numbers of comparisons, calibration significantly improves resolution. For low amplitudes or numbers of comparisons, the ADC performs better without linearity calibration.

Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs

A practical model for characterizing comparator metastability errors in SAR ADCs is presented, and is used to analyze not only the conventional SAR but also LSB-first and asynchronous versions. This work makes three main contributions: first, it is shown that for characterizing metastability it is more reasonable to use input signals with normal or Laplace distributions. Previous work used uniformly-distributed signals in the interest of making derivations easier, but this simplifying assumption overestimated SMR by as much as 18 dB compared to the more reasonable analysis presented here. Second, this work shows that LSB-first SAR ADCs achieve SMR performance equal to or better than conventional SARs with the same metastability window, depending on bandwidth. Finally, the analysis is used to develop a framework for calculating the maximum effective sample rate for asynchronous SAR ADCs, and in doing so demonstrates that proximity detectors are not effective solutions to improving metastability performance.

Practical modeling of comparator metastability for conventional and LSB-first SAR ADCs

A practical model for characterizing comparator metastability errors in SAR ADCs is presented. Previous work used uniformly-distributed ADC input signals to calculate signal-to-metastability error ratio (SMR), in the interest of making the derivation easy. The contributions of this work are three-fold: first, it is shown that for characterizing metastability it is more reasonable to use input signals with normal or Laplace distributions. Second, it is shown that the simplifying assumptions in previous work overestimated SMR by as much as 18dB compared to this more accurate analysis. Finally, it is shown that LSB-first SAR ADCs achieve SMR performance equal to or better than conventional SARs, depending on bandwidth.

A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW

Fully automated Verilog-to-layout synthesis of ADCs using custom analog cells is presented. Previous work in synthesized ADC design used only the standard digital library, and consequently the achieved resolution has been extremely limited. This work adds rudimentary analog components alongside the standard digital library, then uses Verilog code to describe analog functions and synthesize it into layout. The same Verilog code is used to create a MASH ADC in both 65nm and 130nm CMOS, demonstrating 56dB SNDR with ≥2MHz bandwidth. The ADCs occupy 0.014mm2 and 0.046mm2, respectively. Using the same Verilog code demonstrates the rapid portability and scalability of this design procedure.