Manideep Gande

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-μm CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 μ W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC nonlinearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and nonideal traditional multistage ADC structures.

A 10b Ternary SAR ADC with decision time quantization based redundancy

The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.

Blind background calibration of harmonic distortion based on selective sampling

This paper proposes a blind calibration algorithm for suppressing harmonic distortion in analog to digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the harmonic distortion coefficients. The algorithm can be operated in both foreground and background modes to remove even and odd harmonics simultaneously. The algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is harmonic distortion limited. Built in 0.13μm, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB.

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling

This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 μm CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB.

Parallel gain enhancement technique for switched-capacitor circuits

This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters

This paper presents detection and correction methods for single event effects in analog to digital converters. Multi-path ADC based detection method is proposed for single event effects and bit error rate. Two correction schemes are proposed for single event effects based on multi-path ADC structure. Two-path ADC based detection scheme with skip and fill algorithm based correction scheme. Three-path ADC based detection scheme with majority voting based correction scheme. Advantages and limitations of both the methods are presented with simulation results. In particular, the three-path ADC can detect and correct for single event effects independent of repetition rate, magnitude of single event effects and the choice of data converter architecture. In three path ADC technique, the accuracy degradation is less than 1.7 dB or 0.28 bit for the Nyquist bandwidth for single event effects. Bit-Error Rate (BER) is effectively squared for three-path ADC as compared to a conventional ADC.

A 71dB dynamic range third-order ΔΣ TDC using charge-pump

A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.

An interstage correlated double sampling technique for switched-capacitor gain stages

An Interstage Correlated Double Sampling technique is proposed. This new technique avoids the additional thermal noise penalty and the overall feedback factor degradation introduced by the conventional correlated double sampling techniques. In the proposed architecture, a two-stage amplifier is employed and the correlated double sampling is applied to the input of the second gain-stage. The superior noise performance and the gain enhancement of the proposed architecture to the conventional CDS technique is demonstrated in this paper.

A ΔΣ ADC using an LSB-first SAR quantizer

A ΔΣ ADC using an LSB-first quantizer (LSBFQ) is proposed. LSBFQ are energy-efficient ADCs for processing signals with low activity, and have been proposed as standalone quantizers for sensor and biomedical applications. Since the quantizers in highly oversampled multibit ΔΣ ADC process signals with low average activity, the LSBFQ is an ideal quantizer solution. In order to avoid clocking the LSBFQ at a rate much faster than the rest of the ΔΣ ADC, it is proposed that the quantizer be provided a fixed number of comparison cycles, then be interrupted regardless of whether the conversion has fully completed. This is acceptable because for high oversampling ratios (OSR), the average code change is small and an N-bit conversion can usually be completed in fewer than N comparison cycles. In the rare cases that the quantizer is interrupted early, it injects slightly more quantization noise into the loop filter, which is filtered and shaped with little impact on signal-to-noise and distortion ratio (SNDR). Simulation results demonstrate that for high OSR, an LSBFQ achieves higher resolution and lower capacitor switching energy than a conventional SAR ADC using the same number of comparator bitcycles.