Gunrae Kim

Phase transformation of programmed NiSi electrical fuse: Diffusion, agglomeration and thermal stability

An advanced CMOS technology process reliability qualification especially for the NiSi poly gated electrical fuse (eFuse) consists of electrical characterization, physical analyses and reliability evaluations. In this paper, insights are given on microstructural behaviors of the programmed NiSi poly gated eFuse induced by the high temperature storage (HTS) test. Both ex- and in-situ transmission electron microscopy (TEM) reveal that the improved post-resistance of the programmed eFuse is attributed to the low temperature growth of Ni3Si2 during HTS test at 250°C. In addition, the Ni agglomeration, the propensity of Ni3Si2 formation on the programmed eFuse with and without void appearance on the fuse link, is comprehensively investigated in conjunction with the eFuse reliability.

Electromigration of NiSi poly gated electrical fuse and its resistance behaviors induced by high temperature

Insight is given on improved behaviors of the programmed NiSi polygated electrical fuse (eFuse) during the high temperature storage (HTS) test. By using a noble transmission electron microscopy (TEM) that includes scanning transmission electron microscopy (STEM), energy dispersive x-ray spectrometry (EDS), electron energy loss spectrometry (EELS) and nano-beam electron diffraction (NBED), microstructural behavior and phase transition of NiSi in the fuse link are painstakingly investigated before and after HTS test. It is found that improved post-resistance of eFuse is attributed to the low temperature growth of Ni3Si2 induced by HTS test at 250°C, which is microscopically proven by both ex-situ and in-situ TEM. In fact, Ni agglomeration, in which Ni resides around void formed in the fuse link, plays an important role of this cystallization. As results, the root causes of improved post-resistance of eFuse are qualitatively substantiated with respect to dynamic phase transformation and microstructural change in the fuse link.

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

Propensity of Copper Dendrite Growth on Subassembly Package Components Used in Quad Flat Package

Cu dendrite growth of quad flat package linked to epoxy molding compound (EMC), leadframe, and leadframe adhesive tape is comprehensively investigated. Cu dendrite grows particularly in the lead pitch smaller than les 130 mum covering with a leadframe tape, and in turn, it results in a resistive short. Such an appearance is attributed to test procedure of the precondition (30degC/60% relative humidity with 260-degC reflow) followed by biased stress test (125degC/1.95 V), which not only allows moisture condensation in the tape and but also provides bias between the leads. The influences of impurity in EMC and adhesive tape on dendrite formation are quantified with SEM-EDX, Auger electron spectrometry (AES), inductively coupled plasma-mass spectrometry (ICP-MS), and ICP-AES. As a result, the usage of nonhalide EMC can provide more reliable margin than that of larger lead spacing against Cu dendrite growth.

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost

Reliability characterization of 10nm FinFET technology with multi-V T gate stack for low power and high performance

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VTs through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

Development of thermal neutron SER-resilient high-k/metal gate technology

We report the experimental procedure and data that establishes the correlation between natural boron (B10) concentration and thermal neutron soft error rate (SER) in an advanced 28nm high-k/metal gate (HK/MG) technology node. Thermal neutron induced singe event upsets (SEU) depend on the concentration of B10 in the contact process adopted for boosting SRAM performance. However, as technology rapidly evolves in terms of transistor feature size and overall design complexity, B10 concentration needs to decrease so as to reduce thermal neutron SER risk. Optimization of contact and eSiGe process can provide a technology profile that is robust against thermal and high energy neutron SER.

Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance

This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.

New insights into 10nm FinFET BTI and its variation considering the local layout effects

In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized in 10nm compared with 14nm, the BTI and its variation show no obvious differences from the previous node. And this result is further confirmed by SRAM level reliability characterizations. In addition, the impacts of local layout effects on reliability are also investigated. Through Si data, BTI and its variation are not very sensitive to the layout effects which show within about 10% of the differences and the adopted structure for qualification can cover with all the different structures. Moreover, the results are also helpful for the accurate reliability modeling and circuit simulation.

Mature processability and manufacturability by characterizing V T and V min behaviors induced by NBTI and AHTOL test

A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical and electrical characterization and reliability evaluation. By varying the duty cycle of enhanced pulsed radio frequency (eprf) technique used for the gate oxynitridation, the effects of nitrogen concentration and profile at SiO2/Si interface on VT and Vmin shift of thin oxide pMOSFET (∼20A) and SRAM, which result from negative bias temperature stability (NBTI) and accelerated high temperature operating life (AHTOL) stress test, are meticulously investigated. Using secondary ion mass spectrometry (SIMS) and high resolution Rutherford back scattering (H-RBS), nitrogen concentration and profile at the interface are carefully characterized. It is found that pMOSFET device processed with 10% of eprf provides ∼2× longer NBTI lifetimes than with 20% of eprf due to lower nitrogen concentration at the interface. Furthermore, Vmin shift of SRAM with 10% of eprf, which is caused by AHTOL test conditioned at 140°C with 1.4× Vdd, is ∼3∼4× less than with 20% of eprf. In fact, a nano-probing technique elucidates that Vmin shift is mainly attributed to the mismatch of VT between pull-up (PU) transistors in SRAM induced by NBTI stemmed from AHTOL test. It is also empirically shown that Vmin shift behavior is in good agreement with the read margin rather than the write. Accordingly, a stabilized Vmin drift behavior consistently adheres to the write margin. Hence, the optimization of interfacial nitrogen concentration results in less pMOSFET NBTI degradation so as to efficiently suppress Vmin shift of SRAM. Besides, increasing PU transistor size that decreases the γ value (the ratio of Ion current of PG to PU) can also reduce Vmin shift during AHTOL test. Finally, mature processability and manufacturability are attained by characterizing VT and Vmin behaviors for pMOSFET and SRAM from the front-end-of-line (FEOL) process optimization and SRAM bit-cell design aspect.