Joseph Piccirillo

Study of C49‐TiSi2 and C54‐TiSi2 formation on doped polycrystalline silicon using in situ resistance measurements during annealing

In situ resistance versus temperature or time for reactions between 32 and 57.5 nm of titanium and undoped or doped polycrystalline silicon (boron, arsenic, or phosphorus, 7.9×1019–3.0×1020/cm3) has been measured and no clear correlation was found between the activation energy for the formation of the industrially important low‐resistance C54‐TiSi2 phase and its formation temperature. It is also demonstrated that with certain moderate doping levels typical of complementary metal‐oxide‐semiconductor manufacturing, boron or phosphorus‐doped polycrystalline silicon can delay the formation of C54‐TiSi2 more than arsenic‐doped polycrystalline silicon. Finally, by using in situ resistance measurements, it is demonstrated that the ‘‘two‐step’’ thermal annealing process similar to a salicide process requires less thermal annealing time at high temperatures to form C54‐TiSi2 than a single ‘‘one‐step’’ thermal anneal at the same temperature.

Sidewall oxidation of polycrystalline-silicon gate

Evidence is presented demonstrating that sidewall oxidation, a processing step needed for device reliability, can lead to gate oxide thickening in short-channel devices. This increase in thickness is the result of encroachment of birds beaks from the edges of the gate structure into the channel region. The encroachment can be reduced by increasing oxidation temperature and/or using a dry ambient. With a judicious choice of polysilicon sidewall oxidation conditions, minimum gate-to-drain overlap capacitance and adequate device reliability can be achieved.<<ETX>>

Yield improvement for a 3.5-ns BiCMOS technology in a 200-mm manufacturing line

Various issues pertinent to producing high volumes of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The technology consists of a baseline 0.8- mu m CMOS process with four levels of metal and 0.45- mu m L/sub eff/ FETs, to which has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with As-doped polysilicon, and an antimony-doped subcollector. Chips fabricated in the technology include a 3.5-ns 576 K BiCMOS SRAM and a 200 K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, a spurious polysilicon filament, management of the critical emitter window image, and modulation of the titanium silicide/silicon interfacial resistance are considered.<<ETX>>

Nitrogen Profile Engineering in Thin Gate Oxides

In order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 A film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 A chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 A. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Afrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

Effects and prevention of source/drain ion implantation into the polysilicon in a BiCMOS technology

The implantation of source/drain dopants into the polysilicon for FET gates and the bipolar emitter has a profound effect on the operation of the devices. Although the collector current is only slightly affected, the base current increases by as much as a factor of three, with the emitter resistance doubled. The effect of altering the gate doping is evident in the FET devices as well. This paper describes the above device processes necessary to add a silicon nitride blocking layer. >

Optimization of a High-Volume 200-mm BiCMOS Manufacturing Line

Terence Hook, Bomy Chen, Gorden Starkey, Arup Bhattacharyya, Margaret Faucher, Carol Racine, Christa Willets, Steven Eslinger, Subhash Kulkarni, William King, Carol Washburn, Joseph Piccirillo, Steven Mongeon, Arthur Johnson, Edward Gabrielle IBM Technology Products Essex Junction, VT 05452, USA Several issues relevant to yield improvement in a highvolume production of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The baseline technology is a 0.8-pm CMOS process with four levels of metal and 0.45-pm Le, FETs. To this has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with an As-doped polysilicon emitter, and an antimonydoped subcollector. Products fabricated in the technology include a 3.5-ns 576K BiCMOS SRAM and a 200K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, bipolar beta control, an oxide pinhole defect, and control of the titanium silicide sheet resistance are considered.