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Dive into the research topics where Subhash B. Kulkarni is active.

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Featured researches published by Subhash B. Kulkarni.


international symposium on vlsi technology systems and applications | 1993

Yield improvement for a 3.5-ns BiCMOS technology in a 200-mm manufacturing line

Bomy A. Chen; Terence B. Hook; Gorden Seth Starkey; A. Bhattacharyya; Margaret Faucher; C. Racine; Christa R. Willets; Steven Eslinger; Subhash B. Kulkarni; W. King; C. Washburn; Joseph Piccirillo; S. Mongeon; Arthur Johnson; E. Gabrielle

Various issues pertinent to producing high volumes of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The technology consists of a baseline 0.8- mu m CMOS process with four levels of metal and 0.45- mu m L/sub eff/ FETs, to which has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with As-doped polysilicon, and an antimony-doped subcollector. Chips fabricated in the technology include a 3.5-ns 576 K BiCMOS SRAM and a 200 K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, a spurious polysilicon filament, management of the critical emitter window image, and modulation of the titanium silicide/silicon interfacial resistance are considered.<<ETX>>


advanced semiconductor manufacturing conference | 1993

Optimization of a High-Volume 200-mm BiCMOS Manufacturing Line

Terence B. Hook; Bomy A. Chen; Gorden Seth Starkey; Arup Bhattacharyya; Margaret Faucher; Carol Racine; Christa R. Willets; Steven Eslinger; Subhash B. Kulkarni; William King; Carol Washburn; Joseph Piccirillo; Steven Mongeon; Arthur Johnson; Edward Gabrielle

Terence Hook, Bomy Chen, Gorden Starkey, Arup Bhattacharyya, Margaret Faucher, Carol Racine, Christa Willets, Steven Eslinger, Subhash Kulkarni, William King, Carol Washburn, Joseph Piccirillo, Steven Mongeon, Arthur Johnson, Edward Gabrielle IBM Technology Products Essex Junction, VT 05452, USA Several issues relevant to yield improvement in a highvolume production of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The baseline technology is a 0.8-pm CMOS process with four levels of metal and 0.45-pm Le, FETs. To this has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with an As-doped polysilicon emitter, and an antimonydoped subcollector. Products fabricated in the technology include a 3.5-ns 576K BiCMOS SRAM and a 200K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, bipolar beta control, an oxide pinhole defect, and control of the titanium silicide sheet resistance are considered.


Archive | 1995

Semiconductor structure incorporating thin film transistors with undoped cap oxide layers

Bomy A. Chen; Subhash B. Kulkarni; Jerome Bret Lasky; Randy W. Mann; Edward J. Nowak; Werner Rausch; Francis Roger White


Archive | 1997

Semiconductor structure incorporating thin film transistors, and methods for its manufacture

Bomy A. Chen; Subhash B. Kulkarni; Jerome B. Lasky; Randy W. Mann; Edward J. Nowak; Werner Rausch; Francis Roger White


Archive | 2001

Silicon-on-insulator chip having an isolation barrier for reliability

Ronald J. Bolam; Subhash B. Kulkarni; Dominic J. Schepis


Archive | 2003

METHOD TO FILL DEEP TRENCH STRUCTURES WITH VOID-FREE POLYSILICON OR SILICON

Rajiv M. Ranade; Gangadhara S. Mathad; Kevin K. Chan; Subhash B. Kulkarni


Archive | 1997

Field effect transistor having contact layer of transistor gate electrode material

Eric Adler; Subhash B. Kulkarni; Randy W. Mann; Werner Rausch; Luigi Ternullo


Archive | 1998

Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture

Ronald J. Bolam; Subhash B. Kulkarni; Dominic J. Schepis


Archive | 1994

Semiconductor manufacturing process for low dislocation defects

Bomy A. Chen; Terence B. Hook; Subhash B. Kulkarni


Archive | 2004

Method to achieve increased trench depth, independent of CD as defined by lithography

Kevin K. Chan; Subhash B. Kulkarni; Gangadhara S. Mathad; Rajiv M. Ranade

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