Christa R. Willets

Yield improvement for a 3.5-ns BiCMOS technology in a 200-mm manufacturing line

Various issues pertinent to producing high volumes of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The technology consists of a baseline 0.8- mu m CMOS process with four levels of metal and 0.45- mu m L/sub eff/ FETs, to which has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with As-doped polysilicon, and an antimony-doped subcollector. Chips fabricated in the technology include a 3.5-ns 576 K BiCMOS SRAM and a 200 K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, a spurious polysilicon filament, management of the critical emitter window image, and modulation of the titanium silicide/silicon interfacial resistance are considered.<<ETX>>

Effects and prevention of source/drain ion implantation into the polysilicon in a BiCMOS technology

The implantation of source/drain dopants into the polysilicon for FET gates and the bipolar emitter has a profound effect on the operation of the devices. Although the collector current is only slightly affected, the base current increases by as much as a factor of three, with the emitter resistance doubled. The effect of altering the gate doping is evident in the FET devices as well. This paper describes the above device processes necessary to add a silicon nitride blocking layer. >

Optimization of a High-Volume 200-mm BiCMOS Manufacturing Line

Terence Hook, Bomy Chen, Gorden Starkey, Arup Bhattacharyya, Margaret Faucher, Carol Racine, Christa Willets, Steven Eslinger, Subhash Kulkarni, William King, Carol Washburn, Joseph Piccirillo, Steven Mongeon, Arthur Johnson, Edward Gabrielle IBM Technology Products Essex Junction, VT 05452, USA Several issues relevant to yield improvement in a highvolume production of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The baseline technology is a 0.8-pm CMOS process with four levels of metal and 0.45-pm Le, FETs. To this has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with an As-doped polysilicon emitter, and an antimonydoped subcollector. Products fabricated in the technology include a 3.5-ns 576K BiCMOS SRAM and a 200K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, bipolar beta control, an oxide pinhole defect, and control of the titanium silicide sheet resistance are considered.

SiGe HBTs in 90nm BiCMOS technology demonstrating 300GHz/420GHz f T /f MAX through reduced R b and C cb parasitics

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.