Juan Antonio Carballo

Impact of design-manufacturing interface on SoC design methodologies

Todays semiconductor manufacturing trends are increasingly influencing hardware design techniques, tools, and methodologies. We analyze these trends and describe their effects on design methodologies. These effects clearly include impacts on yield optimization resolution enhancement.

A semi-custom voltage-island technique and its application to high-speed serial links

Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000-gate 3.2-Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2V to 0.95V, the chip demonstrates power savings of over 25%.

Value-based Management of Design Reuse

Effective design reuse in electronic products has the potential to provide very large cost savings, substantial time-to-market reduction, and extra sources of revenue. Unfortunately, critical reuse opportunities are often missed because, although they provide clear value to the corporation, they may not benefit the business performance of an internal organization. It is therefore crucial to provide tools to help reuse partners participate in a reuse transaction when the transaction provides value to the corporation as a whole. Value-based Reuse Management (VRM) addresses this challenge by (a) ensuring that all parties can quickly assess the business performance impact of a reuse opportunity, and (b) encouraging high-value reuse opportunities by supplying value-based rewards to potential parties. In this paper we introduce the Value-Based Reuse Management approach and we describe key results on electronic designs that demonstrate its advantages. Our results indicate that Value-Based Reuse Management has the potential to significantly increase the success probability of high-value electronic design reuse.

DFM requirements and solution roadmaps: the multilayer approach

Design For Manufacturability (DFM) has emerged as a major driver as the semiconductor industry continues on its historic scaling trend. The International Technology Roadmap for Semiconductors (ITRS) Design Group has engaged in a major overhaul of the Design Technology Roadmap, including a completely new section focused on DFM. As part of that overhaul, it was observed that quantifying and road-mapping DFM requires effective yet simple models that can relate broad technology characteristics to specific circuit performances such as delay and power. In this article, we discuss the general topic of DFM roadmaps, and show a simple performance model built upon a canonical circuit and analytical solution that is parameterized such that it can address the DFM roadmap problem. We also show that for important model parameters such as threshold voltage, it may be necessary to apportion the various spaces of variability.

The International Conference on Computer Aided Design (ICCAD) Previews Novel Program, External Workshops will Collocate with ICCAD on 10–13 November in San Jose

External Workshops will Collocate with International Conference on Computer Aided Design on 10-13 November , 2008 in San Jose The International Conference on Computer-Aided Design (ICCAD) 2008 will offer 122 outstanding papers split into 40 sessions over three days in San Jose from 10-13 November, plus four half-day tutorials, three embedded tutorials, and two special designer sessions providing additional perspectives. ICCAD will also open its doors to new external workshops which will be collocated with the conference.

Open HW, open design SW, and the VC ecosystem dilemma

The open model for solutions development is quickly extending from software to other technology areas, such as hardware and services. Specifically, just as open source has spawned a revolution in the technical, business, and legal model for software, open hardware will provide a swell of collaborative innovation that will create entirely new markets and provide significant business benefits to the most creative, most reliable, and most adaptable semiconductor, EDA, system-on-chip (SoC) and systems houses. The open-source software stack with Linux as its cornerstone is increasingly the preferred choice for newly venture-funded companies. Open hardware will also change the world of SoC venture investing. While the degree of openness and the business model may vary, SoC products have to be increasingly developed through a collaborative model that helps assemble IP blocks and services from multiple sources. In this paper we describe the open standards model for hardware, chip, and tool innovation, and we argue the a systematic IP valuation methodology will help the success of this environment, in that it will allow each member of the value chain - especially small VC-backed companies - to capture enough value to desire to participate.

Requirement-based design methods for adaptive communications links

High-speed communications link cores must consume low-power, feature, low bit-error-rates (BER), and address many applications. We pFsent a methodology to design adaptive link architectures, whereby the links intemal logic complexity, frequency, and supply are simultaneously adapted to application requirements. The requirement space is mapped to the design space using requirements measurement circuits and configurable logic blocks. CMOS results indicatk that power savings of 60% versus the worst case arc Dossible. while the area overhead is keot under 5%.

Manufacturing-aware design methodologies for mixed-signal communication circuits

Mixed-signal communication circuits are becoming a very common component of systems-on-a-chip as part of modern communication systems. The implementation of DFM and DFT methodologies is critical to enhance communication across the tape-out barrier critical for these circuits. We present a manufacturing-aware design methodology specifically targeting integrated communication circuits in systems-on-a-chip (SoC). The key principle behind the methodology is that flexible design methods which can effectively adjust a design’s power consumption and functionality to its application can also provide critical reductions in manufacturing-induced design risk. The methodology is based on the following four techniques: goal-based design that directly relates top level goals with low level manufacturing-dependent parameters; semi-custom voltage-island physical design techniques; adaptive architecture design; and intelligent on-line at-speed monitoring and problem determination techniques. We describe these four methodology features, and illustrate them on a multi-protocol CMOS 3.2 Gbits/second low-power serial communications core. The presented data shows how this methodology results in better and more cost-effective adaptability of the design to manufacturing and post-manufacturing conditions, thereby improving turnaround time, yield, and overall profit.

Impact of Technology in Power-Grid-Induced Noise

Due to technology scaling, the trend for integrated circuits is towards higher power dissipation, higher frequency and lower supply voltages. As a result, the power supply current delivered through the on-chip power grid is increasing dramatically, which is recognized in the International Technology Roadmap for Semiconductors as a difficult challenge. Early power grid design and the addition of decoupling capacitance have become crucially important to control power-grid-induced noise. We show analytical relationships and simulation results that highlight key relationships between noise and technology parameters. The results underline trends in noise based on current roadmap predictions and reinforce the importance of early planning of global power grids.