Julien Borrel
STMicroelectronics
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Publication
Featured researches published by Julien Borrel.
symposium on vlsi technology | 2015
Julien Borrel; Louis Hutin; Olivier Rozeau; Perrine Batude; Thierry Poiroux; F. Nemouchi; M. Vinet
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (VGS=Vdd=0.7V) increase versus a Titanium liner-based silicidation-free approach.
IEEE Transactions on Electron Devices | 2016
Louis Hutin; Cyrille Le Royer; Robert Pierce Oeflein; S. Martinie; Julien Borrel; V. Delaye; J.M. Hartmann; C. Tabone; M. Vinet
We demonstrate in this paper a fast and simple method for evidencing and classifying the ambipolar response of tunneling-based field effect transistors in pull-down (nFET-like) and pull-up (pFET-like) modes. This technique enables to unequivocally determine whether carrier injection on either side of the device occurs via band-to-band-tunneling or single carrier tunneling through a Schottky barrier. It was applied to Silicon On Insulator (SOI) and SiGeOI tunnel FETs, which were fabricated to be nominally identical, yet showed a discrepancy of several orders of magnitude in ON-state current. The electrostatic analysis of their respective ambipolar signature revealed that the high-drive-current devices were in fact operating like Schottky barrier FETs in the pull-up mode due to a silicidation defect occurring only on the n-doped side. These new findings bring about a reassessment of previously published results in terms of on current--subthreshold swing tradeoff perspectives for nanowire SiGe pTFETs. On the other hand, the resulting unintended asymmetrical device geometry suggests a possible route to fabricating Schottky barrier FETs with reduced parasitic leakage.
international workshop on junction technology | 2014
Louis Hutin; Olivier Rozeau; V. Carron; J.M. Hartmann; Laurent Grenouillet; Julien Borrel; Fabrice Nemouchi; Sylvain Barraud; Cyrille Le Royer; Yves Morand; Christophe Plantier; Perrine Batude; C. Fenouillet-Beranger; Herve Boutry; T. Ernst; M. Vinet
We review in this paper some key enabling process integration modules, the development of which will allow pursuing the trend of energy efficiency improvement in sub-28nm FDSOI technologies.
international workshop on junction technology | 2016
Julien Borrel; Louis Hutin; Helen Grampeix; Emmanuel Nolot; Magali Tessaire; Guillaume Rodriguez; Yves Morand; Fabrice Nemouchi; Magali Gregoire; Emmanuel Dubois; M. Vinet
In this paper, some key fundamental aspects of Metal / Insulator / Semiconductor contacts as well as practical issues occurring with their implementation are reviewed in order to fully comprehend the opportunities and limitations of this approach.
Japanese Journal of Applied Physics | 2017
Julien Borrel; Louis Hutin; Donato Kava; Rémy Gassilloud; N. Bernier; Yves Morand; Fabrice Nemouchi; Magali Gregoire; Emmanuel Dubois; M. Vinet
In this paper, in order to provide a comprehensive overview of the opportunities and limitations of the metal/insulator/semiconductor contacts approach, expected performance based on ideal contact simulations as well as key practical aspects are presented. While the former give us a glimpse of the theoretical potential of this paradigm, mainly to contact nFETs, the latter highlights concerns about the electrical characterization of such contacts along with issues occurring during their physical implementation.
ieee silicon nanoelectronics workshop | 2016
Julien Borrel; Louis Hutin; H. Grampeix; E. Nolot; E. Ghegin; P. Rodriguez; C. Tabone; F. Allain; J.-P. Barnes; Yves Morand; F. Nemouchi; Magali Gregoire; Emmanuel Dubois; M. Vinet
We present experimental and simulated J-V characteristics of Metal/Insulator/Semiconductor (MIS) junctions aiming at improving the contact resistivity for advanced CMOS nodes. We show that an Atomic Layer Deposition (ALD)-based Al2O3 process may induce a native silicon oxide regrowth leading to an additional tunneling resistance in series. A modelling-based analysis of Metal/Insulator/Insulator/Metal (MIIS) contacts, including the potentially beneficial interfacial dipole, provides a new outlook on high-κ/SiO2 bilayers for low resistivity contacts.
Solid-state Electronics | 2016
Louis Hutin; R.P. Oeflein; Julien Borrel; S. Martinie; C. Tabone; C. Le Royer; M. Vinet
IEEE Transactions on Electron Devices | 2016
Julien Borrel; Louis Hutin; Olivier Rozeau; Marie-Anne Jaud; S. Martinie; Magali Gregoire; Emmanuel Dubois; M. Vinet
ieee silicon nanoelectronics workshop | 2015
F. Nemouchi; Louis Hutin; H. Boutry; P. Rodriguez; E. Ghegin; Julien Borrel; Yves Morand; S. Kerdiles; P. Batude; M. Vinet
Archive | 2015
Julien Borrel; Louis Hutin; Yves Morand; Fabrice Nemouchi; Heimanu Niebojewski
Collaboration
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Commissariat à l'énergie atomique et aux énergies alternatives
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