Shinichi Ikenaga

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

In recent years, high density and high speed file memories have become increasingly important for achieving higher performance in computer systems. Multilevel storage dynamic memories offer advantages in terms of speed and density for file usage. An experimental 4Mbit memory has been designed and fabricated utilizing a newly developed multilevel storage scheme and unique peripheral circuits. These include a staircase pulse generator for multilevel storage operation, a voltage regulator for maintaining storage level accuracy, an error correcting circuit for protecting the data from alpha-particle-induced soft error, and a timing generator for testing the device as a fully integrated LSI memory.

The impact of data-line interference noise on DRAM scaling

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond. >

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage bouncings, temperature variation, and threshold-voltage deviation due to the process fluctuation, while maintaining CMOS-DRAM process compatibility. Moreover, feedback-loop stability and frequency response are maintained by ensuring a phase margin of 55° at a unity-gain frequency of 10 MHz using compensation through zero insertion. Implementation of these new circuits in a 16-Mb CMOS DRAM is reported

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized. >

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved. >

A 16-levels/cell dynamic memory

A multilevel storage dynamic memory using a standard DRAM memory cell array is presented. A staircase word pulse and a charge-transfer preamplifier are used for converting binary data to multilevel storage voltages and vice versa. The 16-level (4-bit)/cell READ/WRITE operation has been confirmed at storage levels as low as 80-100 mV. The storage-level voltage accuracy is limited basically by subthreshold leakage current.

New DRAM noise generation under half-V/sub cc/ precharge and its reduction using a transposed amplifier

Dynamic RAM (DRAM) data-line interface noise generated during amplification, the key problem in designing 16 Mbit and higher DRAMs, is investigated. It is reported that: (1) in the half-V/sub cc/ approach, specific combinations of signal types (high and low) and CMOS sense-amplifier operating sequences cause interference noise during amplification; (2) interference noise exists in sense amplifiers; and (3) the noise results in a detrimental effect on data holding time characteristics. The interference noise is overcome by a transposed amplifier structure combined with a transposed data-line structure. >