Shinji Taguchi

Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness

The effects of thinning the FLOTEX EEPROM tunnel oxide on its reliability are investigated using capacitors and cell structures with oxide thickness ranging from 47 to 100 AA. A low-electric-field oxide leakage current is induced by charge injection stressing, and it increases with decreasing oxide thickness. Its conduction mechanism is found to be different from that caused by positive charge accumulation in that it has the opposite thickness dependence. A corresponding increase of charge loss in a write/erase (W/E)-cycled EEPROM cell is observed with decreasing oxide thickness in a room-temperature retention test. When oxide thickness is decreased, the maximum number of W/E cycles to tunnel-oxide breakdown decreases with the decrease in charge to breakdown of the negatively biased gate. For scaling down the EEPROM tunnel oxide, the most serious limiting factor is oxide leakage current induced by W/E cycling stress, resulting in data-retention degradation.<<ETX>>

A new flash-erase EEPROM cell with a sidewall select-gate on its source side

A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability.<<ETX>>

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/Vs, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

A high speed and low power CMOS/SOS multiplier-accumulator

A high speed and low power 16-bit parallel multiplier, with an accumulator on a chip, which performs 16-bit × 16-bit multiplication plus 35-bit data accumulation in 45ns with 125mW power dissipation, is described. The chip uses a unique modified array scheme to reduce the number of adding stages of partial products while constructing a regular structure. The use of CMOS/SOS technology contributes to reductions in the die area (4.2mm square), power dissipation and operation time. Combination of the modified array scheme and CMOS/SOS achieved ECL speed with CMOS power.

A CMOS/SOS multiplier

A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.

A Study of Exchange Anisotropy in Co-CoO Evaporated Thin Films

A systematic study of ferromagnetic-antiferromagnetic coupling in Co-CoO evaporated thin films with thicknesses from 300 to 1400 A has been carried out by measuring hysteresis loops and torque curves in the temperature range from 77 to 630 K. The effect of the cooling conditions on exchange anisotropy is described. The unidirectional anisotropy constant Jk is nearly constant (≈0.1±0.05 erg/cm2) for this thickness range. The external magnetic field is not the essential factor responsible for the exchange anisotropy, but it is the ferromagnetic domain state present which is responsible for the observed loop shift as well as rotational hysteresis loss in torque curves. A model is proposed to account for the observed loop shift, which is supported by the domain observation.

4-&#181;m LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 \times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.

Performance of downward scaled CMOS/SOS

MOS/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS/ SOS devices. Furthermore, short channel CMOS/SOS device performance has been discussed in comparison with the CMOS/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through current between the source and drain. Also, deeper phosphorus implant was used for p-channel MOSFET on SOS to reduce the punch through current. Shallow boron implant was also used to adjust the threshold voltage to the desired value for both n- and p-channel devices. This design is especially beneficial for downward scaled CMOS/SOS devices. Using this device structure, short channel CMOS/SOS devices have been successfully fabricated. Comparison of the experimental results with CMOS/SOS ring oscillator computer simulation has made it clear that the wiring capacitance will play a predominant role in determining the speed of a device with shorter channel length. Superiority of SOS in speed should be emphasized in smaller feature size devices, due to its essentially smaller wiring capacitance than bulk devices.

A 64 kbit MOS dynamic random access memory

A 65536 word/spl times/1 bit dynamic random access memory is developed using 4 /spl mu/m design rules, a 320-/spl Aring/ thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 Kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.