Yuto Ikeda

Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block

Semiconductor memory device with address transition detection and timing control

Shared sense amplifier type semiconductor memory device

Memory device delaying timing of outputting data in a test mode as compared with a normal operating mode

Semiconductor device allowing efficient evaluation of fast operation

Reference voltage generating circuit of semiconductor memory device

Dynamic random access memory device having an improved timing arrangement

Semiconductor memory device and methods for inspecting and manufacturing the same

Speichervorrichtung mit Testfunktion

Dynamic random access memory with read-write signal of shortened duration