Jun Tsukano

Ultra-Thin High-Density LSI Packaging Substrate for Advanced CSPs and SiPs

Abstract An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm2) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm2/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.