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Dive into the research topics where Takehiko Maeda is active.

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Featured researches published by Takehiko Maeda.


Microelectronics Reliability | 2005

Ultra-Thin High-Density LSI Packaging Substrate for Advanced CSPs and SiPs

Tadanori Shimoto; Kazuhiro Baba; Koji Matsui; Jun Tsukano; Takehiko Maeda; Kenji Oyachi

Abstract An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm2) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm2/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.


Japanese Journal of Applied Physics | 2015

Reliability of copper wire bonds on a novel over-pad metallization

Fumiyoshi Kawashiro; Satoshi Itoh; Takehiko Maeda; Tetsuya Hirose; Akira Yajima; Takaki Etoh; Hiroshi Nishikawa

Wire bonding technology is used in most semiconductor products. Recently, high gold prices have forced semiconductor manufacturers to replace Au wires with Cu wires. Because Cu wire bonds are vulnerable to high temperature and humidity, they remain unpopular in automotive and industrial applications with narrow-bond-pad pitches and small deformed ball diameters. To avoid forming the corrosive Cu-rich intermetallic compound Cu9Al4, the use of a Ni/Pd(/Au) over-pad metallization (OPM) structure produced by electroless plating on the Al metallization has been proposed. However, certain technical issues must be overcome, such as variations in the purity and thickness of the plating. To tackle these issues, a novel OPM structure produced by physical vapor deposition is proposed and evaluated in this study.


international conference on electronics packaging | 2014

Effect of isothermal aging on the growth behavior of Cu/Al intermetallic compounds

Omid Mokhtari; Min-Su Kim; Hiroshi Nishikawa; Fumiyoshi Kawashiro; Satoshi Itou; Takehiko Maeda; Tetsuya Hirose; Takaki Eto

This research focuses on the formation and growth behavior of Cu/Al intermetallic compounds (IMCs). In order to investigate IMC growth after 30, 60 and 120 min of aging at 270, 300 and 330 °C, cross-section of Al, Cu and Cu/Al IMCs were examined by scanning electron microscopy (SEM). The results showed that the consumption of the Al layer is more rapid than that of Cu layer, and that after 120 min at 330 °C the Al layer is entirely consumed. The formation of three distinct Cu/Al IMC layers was observed. Scanning transmission electron microscopy (STEM)/energy-dispersive X-ray spectroscopy (EDS) was used to identify the three IMC layers formed at the interface. These were CuAl, Cu3Al2 and Cu9Al4. Also, the activation energies of Cu/Al IMC growth were obtained from an Arrhenius plot.


Archive | 2003

Light thin stacked package semiconductor device and process for fabrication thereof

Takehiko Maeda; Jun Tsukano


Archive | 2007

Wiring board, semiconductor device using wiring board and their manufacturing methods

Katsumi Kikuchi; Shintaro Yamamichi; Hideya Murai; Takuo Funaya; Kentaro Mori; Takehiko Maeda; Hirokazu Honda; Kenta Ogawa; Jun Tsukano


Archive | 2006

Wiring substrate, semiconductor device, and method of manufacturing same

Katsu Kikuchi; Takehiko Maeda; Kenta Ogawa; Jun Tsukano; Shintaro Yamamichi; 武彦 前田; 純 塚野; 健太 小川; 新太郎 山道; 克 菊池


Archive | 2007

WIRING BOARD COMPOSITE BODY, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE WIRING BOARD COMPOSITE BODY AND THE SEMICONDUCTOR DEVICE

Kentaro Mori; Shintaro Yamamichi; Katsumi Kikuchi; Hideya Murai; Takuo Funaya; Takehiko Maeda; Hirokazu Honda; Kenta Ogawa; Jun Tsukano


International symposium on microelectronics | 2003

Ultra-thin high-density packaging substrate for high-performance CSP and SIP

Tadanori Shimoto; Kazuhiro Baba; Hideya Murai; Takehiko Maeda; Keiichiro Kata; Wataru Urano; Hironori Ohta


Transactions of The Japan Institute of Electronics Packaging | 2014

Investigation of Formation and Growth Behavior of Cu/Al Intermetallic Compounds during Isothermal Aging

Omid Mokhtari; Min-Su Kim; Hiroshi Nishikawa; Fumiyoshi Kawashiro; Satoshi Itoh; Takehiko Maeda; Tetsuya Hirose; Takaki Eto


Archive | 2011

Method for manufacturing a semiconductor device having a heat spreader

Yuko Sato; Takehiko Maeda; Fumiyoshi Kawashiro

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