Minjung Jin

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (tbd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, tbd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter tbd than with DC at a lower frequency. This is attributed to hole trapping into IL as Vg is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer tbd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because Gm degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.

Hot carrier reliability characterization in consideration of self-heating in FinFET technology

A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also a higher Ea in PFET HCI), rather than the negative bias temperature instability (NBTI) effect during HCI stress. Furthermore, in order to guarantee the precise estimation of HCI under circuit level AC condition, a new empirical HCI lifetime model decoupled from the SHE is proposed, which is further verified by the Si data from nanosecond pulsed waveform HCI stress and Ring Oscillator stress results.

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.

Reliability characterization of 10nm FinFET technology with multi-V T gate stack for low power and high performance

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VTs through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instability (PBTI) is strongly dependent on the adopted HK stack processes. In this work it is reported, for the first time, a detailed analysis of the nature of the PBTI degradation and recovery under DC and AC conditions by a novel stress and test methodology. Our observations over two HK processes (A & B) support the PBTI physical picture of two uncorrelated independent contributions to the PBTI damage. Namely, electron trap activation in pre-existing (before stress) process induced traps as well as electron traps generation in the HK bulk oxide. It is shown that the relative role of these two components to PBTI aging is strongly process dependent and fully explains the observed DC vs. AC PBTI process sensitivity. This finding challenges the generally expected dependence of AC/DC PBTI Vt shift ratio as function of AC pulse duty cycle. The root cause of such a striking AC and DC PBTI aging differences in these two processes and its implication to technology qualification are discussed in details.

Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

Impact of hydrogen in capping layers on BTI degradation and recovery in high-κ replacement metal gate transistors

Bias Temperature Instability (BTI) degradation and recovery with different types of MOL capping layers are investigated in a 20nm Replacement Metal Gate (RMG) CMOS technology. It is found that less compressive RMG capping layers substantially improve reliability and device performance because of less hydrogen within the RMG capping material. The hydrogen content plays an important role in BTI degradation and recovery. Increased hydrogen enhances interface state generation during NBTI stress and suppresses h+ trap activation. This change in interface states has minimal impact on PBTI.

Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster

The propensity of HCI and BTI degradation of HfSiON MOSFET on strained SiN-CESL performance booster is meticulously investigated. It is found that HCI and BTI lifetime of HfO based n/p MOSFET devices depend on hydrogen, initial Dit and plasma charging inherently related to the stress type of CESL fabricated with PECVD. In case for tensile CESL, n/p MOSFET devices far exceed reliability targets for both HCI and BTI. While compressive CESL on n/p MOSFET drastically depresses HCI and BTI lifetime.

New insights into 10nm FinFET BTI and its variation considering the local layout effects

In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized in 10nm compared with 14nm, the BTI and its variation show no obvious differences from the previous node. And this result is further confirmed by SRAM level reliability characterizations. In addition, the impacts of local layout effects on reliability are also investigated. Through Si data, BTI and its variation are not very sensitive to the layout effects which show within about 10% of the differences and the adopted structure for qualification can cover with all the different structures. Moreover, the results are also helpful for the accurate reliability modeling and circuit simulation.