Siva V. Thyagarajan

A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication

A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.

A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters

We demonstrate a fully-integrated, high-efficiency inverse Class-D power amplifier in 65nm CMOS process. Such efficient switching amplifiers can form the core of digital polar transmitters. A comprehensive analytical framework has been developed to reveal the design trade-offs and enable efficiency maximization. Operating from a 1-V supply, the PA delivers 22dBm output power with a high efficiency of 44% without using any RF process options. The PA efficiency is comparable to that of state-of-the-art CMOS switching PAs, though it uses a much simpler output matching network. The PA has been integrated into a mixed-signal polar transmitter and meets the 802.11g (54Mbps 64QAM OFDM) spectral mask and EVM requirements with more than 18% average efficiency.

A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS

CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is detrimental to the design of RF and mm-wave systems. Higher sensitivity to process variations and inaccuracies in modeling of active and passive devices pose another challenge to the design of these systems at deep submicron technology nodes. This paper describes the design of a 60 GHz power amplifier in 28 nm CMOS technology. A drain-source neutralization technique maintains the stability of the PA and the wideband nature is achieved by the application of low-k transformer networks. The PA comprises of three stages and achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB. Using a two-way transmission line based power combiner, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%.

A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS

Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication. In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology. The receiver employs a direct-conversion mixer-first architecture with an integrated slotted loop antenna. A 240 GHz LO chain drives the passive mixers to down-convert the modulated data to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The receiver has a noise figure of 15 dB with a conversion gain of 25 dB calculated from measurement data. The receiver achieves a data rate of 10 Gbps (with ) and a maximum data rate of 16 Gbps (with BER of 10-4) with a receiver efficiency of 16 pJ/bit.

A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

In this paper, a 240 GHz 16 Gbps QPSK transmitter is demonstrated in 65 nm bulk CMOS process. The transmitter chain employs an 80 GHz local oscillator and a modulator to generate the data that is amplified by a class-E switching power amplifier. The amplified signal then drives the 240 GHz tripler to generate the required modulated data. By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1 dBm. A maximum data rate of 16 Gbps is achieved with a transmitter efficiency of 14 pJ/bit.

A 240GHz wideband QPSK transmitter in 65nm CMOS

This paper demonstrates a 240GHz wideband QPSK transmitter in 65nm bulk CMOS. The proposed transmitter employs an 80GHz local oscillator, a quadrature differential hybrid, and a QPSK modulator. Additionally, an 80GHz class-E switching power amplifier is used to efficiently boost the phase-modulated wideband signal. A frequency tripler then regenerates the modulated signal at 240GHz while preserving the QPSK constellation. By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1dBm. A maximum data rate of 16Gbps is achieved with a total power consumption of 220mW.

A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS

The rapid scaling of CMOS technology in the last decade has enabled the design of high speed and efficient digital CMOS circuits. However, the design of RF and mm-wave systems has become more challenging due to inaccuracies in modeling and increased losses in the active and passive devices. This paper presents the design of a 60 GHz linear wideband power amplifier (PA) in deeply scaled 28 nm CMOS technology. The PA utilizes cascode drain-source neutralization to improve stability and low-k transformer techniques to achieve high bandwidth. Using transmission line power combining, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%. The three stage PA achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB.

A fully-integrated efficient CMOS inverse Class-D power amplifier for digital polar transmitters

In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any RF process options. This is comparable to that of state-of-the-art CMOS switching PAs despite using a much simpler output matching network.

A circuit designer's guide to 5G mm-wave

The fourth generation mobile phone standards (4G) in widespread use include Long Term Evolution (LTE) and LTE-A (Advanced), which support up to 44 bands internationally, or an aggregate bandwidth of about 1 GHz in TDD and FDD modes. Techniques such as carrier aggregation allow the mobile operator to maximize bandwidth and deliver high data rate to users. As demand for wireless connectivity continues to grow exponentially, a fifth generation (5G) standard is envisioned, with the requirement to deliver higher throughputs, more spectrum-particularly in the mm-wave bands-higher capacity through spatial diversity, and lower latency. The projected deployment date of 5G is in 2019, and various proposals are under consideration. This paper will highlight important implications for the design of transceivers for 5G, particularly those targeting the mm-wave bands.

A 240GHz wideband QPSK receiver in 65nm CMOS

This paper demonstrates a 240GHz wideband QPSK receiver in 65nm bulk CMOS. A direct-conversion mixer-first architecture is implemented with a 240GHz on-chip antenna. Wideband passive mixers at the front end employ a 240GHz LO and convert the received signal down to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The 240GHz LO chain consists of 27GHz/80GHz injection-locked oscillators, 80GHz amplifiers and a frequency tripler. The overall receiver gain is 25dB and the noise figure is 15dB from measurements. This receiver design achieves a data rate of 16Gbps with a power consumption of 260mW.