Chan Keun Kwon

An Energy-Efficient Fast Maximum Power Point Tracking Circuit in an 800-μW Photovoltaic Energy Harvester

An energy-efficient maximum power point tracking (MPPT) circuit with a fast-tracking time for use with 800-μW PV energy harvesters is presented in this paper. The proposed MPPT circuit uses a successive approximation register MPPT algorithm, which has a power down mode and a fast tracking time, to achieve low power consumption and energy savings. The prototype MPPT circuit, which consists of analog-based circuits, has been implemented and fabricated in a 0.35-μm BCDiMOS process. The MPPT core occupies an area of 3 mm2 and consumes 4.6 μW of power. The tracking time is reduced by 69.4% and the stored energy is increased by 31.4% as compared to the conventional hill climbing-based MPPT algorithm under indoor conditions.

A CMOS Magnetic Hall Sensor Using a Switched Biasing Amplifier

A compact CMOS magnetic Hall sensor that includes both a Hall plate and readout circuit is proposed. In order to achieve a low-noise and low-power operation, the sensor employs a switched biasing amplifier with a chopper. The prototype has been implemented and fabricated in a high-voltage 0.18 CMOS process and occupies 0.624 mm2. Owing to the switched biasing amplifier, the input-referred noise is reduced from 41 μT√Hz to 25 μT/ √Hz. The entire sensor consumes 4.5 mW with a 3.3 V supply voltage.

Design of Pedestrian Target Selection With Funnel Map for Pedestrian AEB System

Recently, numerous vehicles have been installed with an autonomous emergency braking (AEB) system for protecting pedestrians. This system helps in avoiding or reducing accidents by alerting the driver and controlling the automatic brake actuator before an accident. Moreover, the European New Car Assessment Program (NCAP) has stipulated AEB pedestrian systems as a standard requirement since 2016. This paper presents pedestrian target selection using a funnel map for a pedestrian AEB system. The concept of target selection is based on crash probability calculations by comparing the pedestrians predicted position and the current position to deduce the vehicle speed before an accident occurs. It is necessary to allow early breaking to avoid an accident. To determine the precise warning and brake timing, the warning distance is calculated using the vehicle and sensor fusion information. The pedestrian target selection algorithm is tested using a real vehicle on a test track in three different scenarios for the Euro NCAP using a pedestrian dummy authorized by the Euro NCAP. Upon comparing the results before and after the application of the proposed algorithm, the longitudinal distance is shown to have a maximum margin of 1.5 m, and the vehicle speed has a maximum reduction effect of 24.7 km/h. Test results show that the proposed pedestrian AEB system can avoid or mitigate an accident when the vehicle travels at speeds up to 40 km/h.

Simulation of serpentine trace of DQ PCB layout for DDR3 applications

This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.

A 0.4-mW, 4.7-ps Resolution Single-Loop

A compact, low-power, single-loop third-order delta-sigma (ΔΣ) time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution (ΔΣ) TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm2, consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.

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A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-μm CMOS process with an active area of 2.445mm2, which achieves a differential non linearity (DNL) of 0.25LSB and an integral non-linearity (INL) of 0.19LSB. Additionally, the SFDR increases by 13.2dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176mW from a 1.8-V supply voltage.

TDC Using a Half-Delay Time Integrator

The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

A 12-bit 500-MS/s current steering CMOS DAC for high-speed PLC modems

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

Practical Approach to Power Integrity-Driven Design Process for Power-Delivery Networks

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .

A wideband cmos cascaded variable gain amplifier using unequally distributed gain control for DVB-S.2 receiver

This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.