Junji Koga

Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique

A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

This paper proposes, for the first time, the concept of programmable logic circuit realized with single-electron transistors (SETs). An SET having nonvolatile memory function is a key element for the programmable SET logic. The writing and erasing operations of the nonvolatile memory function make it possible to tune the phase of Coulomb oscillations. The half-period phase shift induced by the memory function makes the function of SETs complementary to that of the conventional SETs. As a result, SETs having nonvolatile memory function have the functionality of both the conventional (nMOS-like) SETs and the complementary (pMOS-like) SETs. By utilizing this fact, the function of SET circuits can be programmed with great flexibility, on the basis of the information stored by the memory functions. We have successfully fabricated SETs that operate at room temperature and observed the highest room-temperature peak-to-valley current ratio of Coulomb oscillations. The operation of the programmable SET logic is demonstrated using the room-temperature operating SETs. This is the first demonstration of room-temperature SET logic operation. The proposed programmable SET logic provides the potential for low-power, intelligent LSI chips suitable for mobile applications.

High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions

High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky barrier transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi/sub 2/ process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology

We have proposed a new MOSFET structure, strained-Si/Si/sub 0.9/Ge/sub 0.1/-on-Insulator (SSGOI) MOSFETs applicable to the sub-100 nm generation. This SSGOI structure was successfully fabricated by the combination of SIMOX technology and the Si re-growth technique. The strained-Si in SSGOI was found to have good crystal quality and very flat interfaces. SSGOI p-MOSFETs exhibited good FET characteristics. It was demonstrated, for the first time, that the hole mobility of the SSGOI p-MOSFETs is higher that of the universal mobility of conventional Si p-MOSFETs.

Subband structure engineering for performance enhancement of Si MOSFETs

This paper presents a new strategy to enhance the current drive of Si MOSFETs, utilizing a subband structure engineering. It is found that SOI MOSFETs with SOI thickness thinner than the inversion layer of bulk MOSFETs can provide higher current drive than bulk MOSFETs, because of the significant modulation of the subband structure. This performance enhancement is attributed to the increase in both the inversion-layer mobility and the inversion-layer capacitance.

Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering

The carrier transport mechanisms in single- and double-gate UTB MOSFETs are investigated. It is demonstrated that Coulomb scattering in UTB MOSFETs is greater than that in thicker body MOSFETs. It is found that, in higher Ns regions, the mobility of double-gate structures is smaller than that of single-gate structures in 4.3-nm body MOSFETs, which is due to the SOI-thickness-fluctuation-induced scattering. It is also demonstrated that Coulomb scattering is greatly suppressed in double-gate MOSFETs. The electrical characteristics of sub-1-nm body MOSFETs are also investigated.