Ryuji Ohba

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

This paper proposes, for the first time, the concept of programmable logic circuit realized with single-electron transistors (SETs). An SET having nonvolatile memory function is a key element for the programmable SET logic. The writing and erasing operations of the nonvolatile memory function make it possible to tune the phase of Coulomb oscillations. The half-period phase shift induced by the memory function makes the function of SETs complementary to that of the conventional SETs. As a result, SETs having nonvolatile memory function have the functionality of both the conventional (nMOS-like) SETs and the complementary (pMOS-like) SETs. By utilizing this fact, the function of SET circuits can be programmed with great flexibility, on the basis of the information stored by the memory functions. We have successfully fabricated SETs that operate at room temperature and observed the highest room-temperature peak-to-valley current ratio of Coulomb oscillations. The operation of the programmable SET logic is demonstrated using the room-temperature operating SETs. This is the first demonstration of room-temperature SET logic operation. The proposed programmable SET logic provides the potential for low-power, intelligent LSI chips suitable for mobile applications.

Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs

The characteristics of ultrathin-body (UTB) SOI MOSFETs, whose SOI-channel thickness T/sub SOI/ is thinner than the inversion-layer thickness of bulk MOSFETs, are investigated. It is found for the first time that at low temperatures (<50 K) the mobility of the UTB MOSFETs coincides with that of thicker body SOI MOSFETs in spite of the fact that at room temperature the mobility of UTB MOSFETs decreases as T/sub SOI/ decreases. It is experimentally demonstrated for the first time that the gate-channel capacitance of the UTB MOSFETs increases as T/sub SOI/ decreases. In addition, it is demonstrated that the physical origins of the threshold voltage increase in UTB MOSFETs can be categorized as mobility degradation and a subband energy level increase. All these results are consistently explained in terms of quanturn-mechanical effects.

Nonstationary electron/hole transport in sub-0.1 /spl mu/m MOS devices: correlation with mobility and low-power CMOS application

We have experimentally studied the high-lateral-field carrier velocity near the source edge in sub-0.1 /spl mu/m MOSFETs. It is demonstrated that the high-field electron velocity and hole velocity have universal low-field mobility dependence. This shows that the hole velocity is lower than the electron velocity due to the holes lower mobility. Moreover, we have investigated the low-power CMOS operation using the velocity overshoot. It is verified that there is a most suitable supply voltage for improving the CMOS operation using velocity overshoot. The most suitable supply voltage is shown to be about 1 V. Therefore, the velocity overshoot will be very useful for low voltage CMOS operation in the future.

Programmable single-electron transistor logic for low-power intelligent Si LSI

Room-temperature-operating single-electron devices work not only as single-electron transistors (SETs) but also as nonvolatile single-electron memories. It is demonstrated that the combination of Coulomb oscillations with the nonvolatile memory functions offers high programmability for LSIs. The power and delay of a programmable SET logic are estimated.

Silicon single-electron tunneling device fabricated in an undulated ultrathin silicon-on-insulator film

We report on a silicon single-electron tunneling device fabricated in an ultrathin (∼3 nm) silicon-on-insulator (SOI) film whose surface is undulated by an alkaline-based solution. The nanometer-scaled undulation in the ultrathin film results in great SOI thickness variations and brings about large electron-potential fluctuations, due to the difference of the quantum confinement effects from one part to another. Consequently, a number of quantum dots are effectively formed in the undulated ultrathin SOI film. This device shows clear Coulomb blockade oscillations at 80 K, as well as nonvolatile single-electron memory functions even at room temperature. The measurements of the undulation with atomic force microscopy reveal that the undulation has two correlation lengths. Based on the analysis of electrical characteristics, it is concluded that the Coulomb blockade oscillations are dominated by a quantum dot formed by the longer-correlation-length undulation and that single-electron memory effects are due to...

Room-temperature operation of multifunctional single-electron transistor logic

Successfully fabricated SETs operating at room temperature with the highest peak-to-valley current ratio (PVCR) ever reported, and demonstrated, for the first time, the room-temperature operation of a SET/CMOS hybrid circuit. In addition, the authors have verified that the function of a SET-pMOS circuit can be programmed from a converter/inverter to an inverter/converter by utilizing a nonvolatile memory function incorporated in the SET, suggesting that the programmable multiple functionality will be realized in logic circuits consisting of SETs with a nonvolatile memory function. These results open a new way to the realization of future low-power super-design-flexible field-programmable logic LSIs by using SETs having a memory function.

1200μm 2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application

In this work, because of the high-amplitude random noise at high frequency from the SiN MOSFET, we need only a single amplifier and A/D converter, and the amplifier area is decreased.

Physical random number generator based on MOS structure after soft breakdown

We present a novel physical random number generator (RNG) that uses a metal-oxide semiconductor (MOS) capacitor after soft breakdown (SBD) as a random source. It is known that the electrical properties of MOS capacitors after SBD show large fluctuation. When the resistor in an astable multivibrator is replaced with an MOS capacitor after SBD, the multivibrator converts the noise signal into a rectangular wave whose period fluctuates randomly. A 1-bit counter and a flip-flop are used to generate random numbers from the fluctuating rectangular wave. Some high-level tests indicate that the generated random numbers have excellent quality for cryptographic applications. Even though our circuit is small and can be constructed using about 20 complementary-MOS logic gates and several passive devices, high-quality random numbers such as those generated by large physical RNGs can be obtained.

Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory

The carrier charging/discharging characteristics in a multidot Si nanocrystal floating gate memory are investigated by measuring the gate current directly. To detect a small gate current, we use a large device-size memory. In the gate current characteristics, double peak structures, with one of the peaks at the threshold voltage and the other at the flat-band voltage, are found. The separation into two peaks is shown to be due to the change of the charging/discharging carrier sources between the source/drain and the substrate in the channel depletion region. These show that the carrier charging/discharging characteristics change critically at each of the threshold voltage and the flat-band voltage. Charging/discharging rate reduction due to the surface potential flexibility and the carrier number shortage in the channel depletion region is proposed to explain the critical changes.