Junrui Qin

Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

Concepts of effective sensitive area and effective SET pulse width are proposed to model the actual sensitive area. Simulation results present that the soft error vulnerabilities got by using the effective sensitive area can be almost an order larger than the ones got by using the normal approach when the ion LET is 30 MeV ·cm2/mg. And heavy-ion experiments are conducted to demonstrate the simulation results.

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

This paper reports on the supply voltage dependency of single-event transient (SET) propagation and multinode charge collection phenomena in integrated circuits. We have found that the SET pulsewidth propagating to subsequent stages in a circuit may decrease with reduced power supply voltage, which runs counter to the general conclusion that ultralow power applications are much more susceptible to disruption from a particle strike. This effect provides the circuit designers a guidance to reconsider the impact of voltage on SET pulsewidth.

Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process

Through revising the process of charge collection for reversed drain-bulk junction, a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS. The model can capture the plateau effect, and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation. Considering the case of connecting load, it is still valid. For combination and sequential logic circuits, the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

The sensitivity of single-event effects (SEEs) in nanoscale CMOS for body-biasing circuits has been investigated. For PMOS hits, it is found that forward-biasing the body for high-speed applications can suppress the SET pulses greatly. Reverse-biasing the body for low-power applications, however, does not reduce the SEE vulnerability compared with operation when the body grounded. The body-biasing voltage has no impact on SEE sensitivity for NMOS hits.