Biwei Liu

Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.

Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source isolation is studied by way of technology-computer-aided-design numerical simulations. The source-isolation layout design methodology is thoroughly discussed for the combinational standard cell. Based on a 90-nm twin-well CMOS technology, the simulation results indicate that the proposed “radiation hardened by design” (RHBD) technique can significantly reduce SET pulsewidth. The effects of the ion strike angles and strike locations on this hardened technique are also studied, and the area penalty is also discussed. When we combine the layout technique that utilizes the quenching effect with the proposed source-isolation layout technique, the RHBD standard-cell library can be further exploited for additional P-hit SET mitigation in the spaceborne integrated-circuit design.

Temperature Dependency of Charge Sharing and MBU Sensitivity in 130-nm CMOS Technology

This paper investigates the temperature dependency of charge sharing in 130-nm CMOS technology over a temperature range of 200 to 420 K. TCAD simulation results show the charge sharing collection increases significantly with temperature rising, which is 65% ~ 317%. The LETth of MBU in two SRAM cells is also quantified. The result reveals that the upset LETth of the passive cell decreases in the whole temperature range, which is different from the parabolic relationship of single-event upsets temperature dependency.

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

Concepts of effective sensitive area and effective SET pulse width are proposed to model the actual sensitive area. Simulation results present that the soft error vulnerabilities got by using the effective sensitive area can be almost an order larger than the ones got by using the normal approach when the ion LET is 30 MeV ·cm2/mg. And heavy-ion experiments are conducted to demonstrate the simulation results.

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.

Single-Event Pulse Broadening After Narrowing Effect in Nano-CMOS Logic Circuits

In nanometer bulk CMOS processes, the multinode charge collection induced by single events (SEs) is becoming prevalent. Our research indicates that the SE transient (SET) pulse evolvement is more intricate with a small feature size due to the multinode charge collection. The generated SET can be quenched due to charge sharing, and the quenched SET can be obviously broadened again due to charge sharing as well. This phenomenon is named as the pulse broadening after narrowing (PBAN) effect. The neutron simulations by Geant4 indicate that the PBAN effect is becoming more and more remarkable with the technology scaling down and that the elastic collision is the dominant effect for atmospheric neutron radiation, whereas the inelastic collision plays a dominant role on a monoenergetic neutron strike with energy larger than 10 MeV.

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

This paper reports on the supply voltage dependency of single-event transient (SET) propagation and multinode charge collection phenomena in integrated circuits. We have found that the SET pulsewidth propagating to subsequent stages in a circuit may decrease with reduced power supply voltage, which runs counter to the general conclusion that ultralow power applications are much more susceptible to disruption from a particle strike. This effect provides the circuit designers a guidance to reconsider the impact of voltage on SET pulsewidth.

Characterization of Single-Event Transient Pulse Broadening Effect in 65 nm Bulk Inverter Chains Using Heavy Ion Microbeam

The propagation induced pulse broadening (PIPB) effect of the SET pulses in 65nm bulk inverter chains is characterized and discussed generated by the heavy ion microbeam. An odd-even separated layout placement strategy is implemented in the test chip to improve the resolution of the broadened width measurement. The experiment results show that bigger transistor size is able to inhibit the PIPB effect better, but the well structure and layout topology show insignificant influence on the PIPB effect of the SET pulses generated by the low LET heavy ions.

Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process

Through revising the process of charge collection for reversed drain-bulk junction, a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS. The model can capture the plateau effect, and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation. Considering the case of connecting load, it is still valid. For combination and sequential logic circuits, the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.

Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

The advancement in the process leads to more concern about the Single Event (SE) sensitivity of the Differential Cascade Voltage Switch Logic (DCVSL) circuits. The simulation results indicate that the Single Event Transient (SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.摘要创新点本文基于65nm双阱工艺, 对差分逻辑与普通逻辑单粒子瞬态(SET)响应进行了对照研究。 研究表明受交叉耦合结构的影响, 差分逻辑SET响应与普通逻辑有很大的差异。 为了有效阐释差分逻辑SET随器件因素和环境因素的变化规律, 本文提出了有效收集时间理论。 本文认为晶体管敏感区电荷收集的时间可分为受限收集时间、自由收集时间和残余收集时间; 其中受限收集时间和自由收集时间对SET脉冲宽度其决定性作用。 对于普通逻辑, 粒子入射能量较高时, 受限收集时间支配着SET脉冲宽度; 然而对于差分逻辑, 当脉冲反馈特性较强时, 自由收集时间对SET的贡献接近于受限收集时间。 因而在设计差分逻辑电路时, 有必要适当选择晶体管尺寸, 调节脉冲反馈特性, 从而有效抑制SET。