Yibai He

Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.

Flip-flops soft error rate evaluation approach considering internal single-event transient

The internal single-event transient (SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate (SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data.

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

This paper reports on the supply voltage dependency of single-event transient (SET) propagation and multinode charge collection phenomena in integrated circuits. We have found that the SET pulsewidth propagating to subsequent stages in a circuit may decrease with reduced power supply voltage, which runs counter to the general conclusion that ultralow power applications are much more susceptible to disruption from a particle strike. This effect provides the circuit designers a guidance to reconsider the impact of voltage on SET pulsewidth.

A Scan Chain Based SEU Test Method for Microprocessors

A test method based on the scan chain technique is proposed to evaluate the single event upset performance for all the flip-flops in the microprocessors. The single event upset (SEU) performance of a digital signal processor is evaluated using the proposed method and program test method with different working frequencies. Heavy ion irradiation experiment results show that this method is able to capture all the SEUs in the whole chip with no escape and has few infections from the single event transients, which is helpful to study the SEUs precisely in the complicated processors.