Shuming Chen

Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.

Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source isolation is studied by way of technology-computer-aided-design numerical simulations. The source-isolation layout design methodology is thoroughly discussed for the combinational standard cell. Based on a 90-nm twin-well CMOS technology, the simulation results indicate that the proposed “radiation hardened by design” (RHBD) technique can significantly reduce SET pulsewidth. The effects of the ion strike angles and strike locations on this hardened technique are also studied, and the area penalty is also discussed. When we combine the layout technique that utilizes the quenching effect with the proposed source-isolation layout technique, the RHBD standard-cell library can be further exploited for additional P-hit SET mitigation in the spaceborne integrated-circuit design.

Temperature Dependency of Charge Sharing and MBU Sensitivity in 130-nm CMOS Technology

This paper investigates the temperature dependency of charge sharing in 130-nm CMOS technology over a temperature range of 200 to 420 K. TCAD simulation results show the charge sharing collection increases significantly with temperature rising, which is 65% ~ 317%. The LETth of MBU in two SRAM cells is also quantified. The result reveals that the upset LETth of the passive cell decreases in the whole temperature range, which is different from the parabolic relationship of single-event upsets temperature dependency.

Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism

Abstract The impact of the source on single event transient (SET) is studied for the balanced two-transistor inverter by a novel simulation structure in a 90xa0nm twin-well bulk CMOS technology. Due to the significantly distinct mechanism of single event change collection in PMOS and NMOS, the source, which is beneficial to broadening P-hit SET pulse width ( W SET ) but reducing N-hit W SET , plays a different role in SET production. Based on these different source roles, different radiation hardened by design (RHBD) methods are proposed to reduce W SET for PMOS and NMOS, respectively. The simulation results show that the proposed RHBD methods can remarkably reduce W SET .

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

Concepts of effective sensitive area and effective SET pulse width are proposed to model the actual sensitive area. Simulation results present that the soft error vulnerabilities got by using the effective sensitive area can be almost an order larger than the ones got by using the normal approach when the ion LET is 30 MeV ·cm2/mg. And heavy-ion experiments are conducted to demonstrate the simulation results.

Novel Layout Technique for N-Hit Single-Event Transient Mitigation via Source-Extension

In this paper, a novel layout technique for N-hit single-event transient (SET) mitigation that is based on source-extension is proposed. Based on 65 nm bulk CMOS technology, both mixed-mode numerical simulations with technology computer-aided design (TCAD), as well as heavy-ion experiments show SET pulse widths are efficiently reduced with source extension. As opposed to what is found in the P-hit SET production process, where the source plays a detrimental role in SET mitigation due to the well-known bipolar effect, in the N-hit SET production process the source plays a beneficial role in reducing SET pulse widths, attributable to a parasitic reversed bipolar effect. This effect will be discussed in depth in this paper, and the proposed radiation hardened by design (RHBD) layout technique will be extended to common combinational standard cells. The area penalty will also be discussed for the proposed layout technique. Meanwhile, both the P-hit and N-hit SET mitigation layout techniques will be introduced into the standard inverter layout, and the final improvement in SET pulse width will be discussed.

Heavy-Ion-Induced Charge Sharing Measurement With a Novel Uniform Vertical Inverter Chains (UniVIC) SEMT Test Structure

In this paper, a novel uniform vertical inverter chains (UniVIC) single event multiple transient (SEMT) test structure is proposed for the first time. Charge sharing between standard inverters is measured for the first time experimentally. The heavy-ion experiment results in 65 nm bulk CMOS process indicate that charge sharing can impact three transistors at most. At the same time, the occurring probability of charge sharing is attained for the first time experimentally. 3D TCAD simulations have also verified them. In total, the conclusions are helpful for researchers to have a direct knowledge of charge sharing in concrete circuits, and then to improve the precise of soft error evaluation.

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.

Single-Event Pulse Broadening After Narrowing Effect in Nano-CMOS Logic Circuits

In nanometer bulk CMOS processes, the multinode charge collection induced by single events (SEs) is becoming prevalent. Our research indicates that the SE transient (SET) pulse evolvement is more intricate with a small feature size due to the multinode charge collection. The generated SET can be quenched due to charge sharing, and the quenched SET can be obviously broadened again due to charge sharing as well. This phenomenon is named as the pulse broadening after narrowing (PBAN) effect. The neutron simulations by Geant4 indicate that the PBAN effect is becoming more and more remarkable with the technology scaling down and that the elastic collision is the dominant effect for atmospheric neutron radiation, whereas the inelastic collision plays a dominant role on a monoenergetic neutron strike with energy larger than 10 MeV.

Flip-flops soft error rate evaluation approach considering internal single-event transient

The internal single-event transient (SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate (SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data.