Yankang Du

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

Concepts of effective sensitive area and effective SET pulse width are proposed to model the actual sensitive area. Simulation results present that the soft error vulnerabilities got by using the effective sensitive area can be almost an order larger than the ones got by using the normal approach when the ion LET is 30 MeV ·cm2/mg. And heavy-ion experiments are conducted to demonstrate the simulation results.

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.

Flip-flops soft error rate evaluation approach considering internal single-event transient

The internal single-event transient (SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate (SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data.

A Layout-Level Approach to Evaluate and Mitigate the Sensitive Areas of Multiple SETs in Combinational Circuits

Multiple single-event transients (MSETs) are evaluated from the perspective of sensitive area. First, a simple model is proposed to analyze the sensitive area of simple logic cells. Based on this simple model, the vulnerabilities of MSETs sensitive areas are then calculated. At last, a layout-level approach is designed to reduce the vulnerabilities of the MSETs sensitive areas. Our simulation results present that this layout-level approach could efficiently reduce the occurrence chance of MSETs.

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

This paper reports on the supply voltage dependency of single-event transient (SET) propagation and multinode charge collection phenomena in integrated circuits. We have found that the SET pulsewidth propagating to subsequent stages in a circuit may decrease with reduced power supply voltage, which runs counter to the general conclusion that ultralow power applications are much more susceptible to disruption from a particle strike. This effect provides the circuit designers a guidance to reconsider the impact of voltage on SET pulsewidth.

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

The sensitivity of single-event effects (SEEs) in nanoscale CMOS for body-biasing circuits has been investigated. For PMOS hits, it is found that forward-biasing the body for high-speed applications can suppress the SET pulses greatly. Reverse-biasing the body for low-power applications, however, does not reduce the SEE vulnerability compared with operation when the body grounded. The body-biasing voltage has no impact on SEE sensitivity for NMOS hits.