Arindam Mallik

The economic impact of EUV lithography on critical process modules

Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography be on the forefront of dimensional scaling for the semiconductor industry. Unfortunately, the roadmap for lithography is currently at a juncture of a major paradigm shift. EUV Lithography is steadily maturing but not fully ready to be inserted into HVM. Unfortunately, there are no alternative litho candidates on the horizon that can take over from 193nm. As a result, it is important to look into the insertion point of EUV that would be ideal for the industry from an economical perspective. This paper details the benefit observed by such a transition. Furthermore, it looks into such detail with an EUV throughput sensitivity study.

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

Maintaining Moore’s law: enabling cost-friendly dimensional scaling

Moores Law (Moores Observation) has been driving the progress in semiconductor technology for the past 50 years. The semiconductor industry is at a juncture where significant increase in manufacturing cost is foreseen to sustain the past trend of dimensional scaling. At N10 and N7 technology nodes, the industry is struggling to find a cost-friendly solution. At a device level, technologists have come up with novel devices (finFET, Gate-All-Around), material innovations (SiGe, Ge) to boost performance and reduce power consumption. On the other hand, from the patterning side, the relative slow ramp-up of alternative lithography technologies like EUVL and DSA pushes the industry to adopt a severely multi-patterning-based solution. Both of these technological transformations have a big impact on die yield and eventually die cost. This paper is aimed to analyze the impact on manufacturing cost to keep the Moore’s law alive. We have proposed and analyzed various patterning schemes that can enable cost-friendly scaling. We evaluated the impact of EUVL introduction on tackling the high cost of manufacturing. The primary objective of this paper is to maintain Moore’s scaling from a patterning perspective and analyzing EUV lithography introduction at a die level.

The need for EUV lithography at advanced technology for sustainable wafer cost

Extreme Ultra-Violet lithography (EUVL) is considered as the most promising candidate to replace optical lithography from the 14nm technology node onwards. EUVL has recently been supplanted by multiple patterning using existing 193nm immersion lithography tools for upcoming 14 nm technology node due to the current resolution limitations and production level efficiency restrictions. In this paper, a wafer cost model for technology node from 28nm down to 14nm has been developed. It identifies lithography module as the key component where innovation can be leveraged to reduce cost. The results presented in the paper reveal that wafer cost will be increased by 30% from 28nm to 20nm technology node. A 70% increase in wafer cost is foreseen during a transition from 20nm to 14nm node based on 193nm immersion lithography and multiple patterning. The cost analysis predicts a 30% wafer cost reduction by adapting EUVL at a 14 nm technology node compared to 193nm immersion technology (normalized to 28nm wafer cost). It proves that the readiness of EUVL is critical to keep scale the logic devices at the pace of Moore’s law without violating the scale of economics in semiconductor industry.

Improved cost-effectiveness of the block co-polymer anneal process for DSA

This manuscript first presents a cost model to compare the cost of ownership of DSA and SAQP for a typical front end of line (FEoL) line patterning exercise. Then, we proceed to a feasibility study of using a vertical furnace to batch anneal the block co-polymer for DSA applications. We show that the defect performance of such a batch anneal process is comparable to the process of record anneal methods. This helps in increasing the cost benefit for DSA compared to the conventional multiple patterning approaches.

Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform

This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations. Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers. In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.

EUVL Gen 2.0: key requirements for constraining semiconductor cost in advanced technology node manufacturing

The constant improvement of critical pitch reduction to enable the next generation semiconductor technology node is the primary driver for innovation in semiconductor industry. Previous researches [1] have shown the benefits of EUVL to bring down the wafer manufacturing cost for imec 7nm technology node. Beyond the technology node (N node) that will use EUV single patterning to enable the critical layers, the critical pitch enablement would require the second generation of EUVL lithography (high NA EUV) or double patterning EUVL(EUVL-DP). In this paper, we have provided a comparison between the two alternatives in terms of cost. We explored patterning options that would enable a costfriendly 5nm logic (N+1 node). The goal is to analyze the alternatives beyond the current 0.33 NA EUVL single patterning limit.

Self-aligned block technology: a step toward further scaling

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.