Juri Lee

Comparison of motor-evoked potentials monitoring in response to transcranial electrical stimulation in subjects undergoing neurosurgery with partial vs no neuromuscular block†

BACKGROUND There have been no evidence-based comparisons of motor-evoked potential (MEP) monitoring with no and partial neuromuscular block (NMB). We compared the effects of different levels of NMB including no NMB on MEP parameters. METHODS MEP-monitored 120 patients undergoing neurosurgery were enrolled. The patients were randomly allocated to four groups: Group A was to maintain two train-of-four (TOF) counts; Group B was to maintain a T(1)/Tc of 0.5; Group C was to maintain a T(2)/Tc of 0.5 (T(1,2), first or second twitch height of TOF; Tc, control twitch height); Group D did not maintain NMB. The mean MEP amplitude, coefficient of variation (CV), the incidence of spontaneous respiration or movement, the efficacy of MEP, and haemodynamic parameters were compared. RESULTS The median [inter-quartile range (IQR)] amplitudes of the left leg for Groups A, B, C, and D were 0.23 (0.15-0.57), 0.44 (0.19-0.79), 0.28 (0.15-0.75), and 0.75 (0.39-1.35) mV, respectively. The median (IQR) CVs of the left leg were 71.1 (56.9-88.8), 76.1 (54.2-93.1), 59.8 (48.6-95.6), and 25.2 (17.3-35.0), respectively. The differences between groups of the mean amplitudes of the left arm and both legs were statistically significant (Kruskal-Wallis test, P=0.011 for the left leg). For all limbs, the differences between groups of the CVs were significant (P<0.001, for the left leg). Other parameters were not different. CONCLUSIONS If NMB is used during MEP monitoring, a target T(2)/Tc of 0.5 is recommended. In terms of the MEP amplitude and variability, no NMB was more desirable than any level of partial NMB.

The role of arthroscopic synovectomy in patients with undifferentiated chronic monoarthritis of the wrist

We investigated the clinical response to arthroscopic synovectomy in patients with undifferentiated chronic monoarthritis (UCMA) of the wrist. Arthroscopic synovectomy was performed on 20 wrists in 20 patients with UCMA of the wrist who had not responded to non-steroidal anti-inflammatory drugs. The mean duration of symptoms at the time of surgery was 4.3 months (3 to 7) and the mean follow-up was 51.8 months (24 to 94). Inflamed synovium was completely removed from the radiocarpal, midcarpal and distal radioulnar joints using more portals than normal. After surgery, nine patients had early remission of synovitis and 11 with uncontrolled synovitis received antirheumatic medication. Overall, there was significant improvement in terms of pain relief, range of movement and Mayo score. Radiological deterioration was seen in five patients who were diagnosed as having rheumatoid arthritis during the follow-up period. Lymphoid follicles and severe lymphocyte infiltration were seen more often in synovial biopsies from patients with uncontrolled synovitis. These results suggest that arthroscopic synovectomy provides pain relief and functional improvement, and allows rapid resolution of synovitis in about half of patients with UCMA of the wrist.

An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-

An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.

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This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in 0.13μm CMOS technology. The chip area was 760 × 280 μ㎡.

W Leakage-Compensated PLL and Automatic Quench Waveform Generator

This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose a capacitance-tovoltage converter circuit that measures the capacitance value of the capacitive sensor with the high accuracy and linearity. In this paper, the linearity of the analog front end is guaranteed using full-analog gain and an offset calibration circuit. The proposed design is implemented using CMOS 0.35 μm technology with an active area of 1.94 mm x 1.94 mm. The full output range is from 0.5 to 4.5 V. The ratiometricity is within ±0.7% when the supply voltage is changed by ±10%. The power consumption is 25 mW from a 5 V supply. The output accuracy is within ±1% with respect to Process, Voltage, Temperature variations.

Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in 0.13 ㎜ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum 98.1 ㏈Ω gain and an input current noise level of about 37.8 ㎀/㎐. The die area of the fabricated TIA is 1.9 ㎜ x 2.2 ㎜ for 4-channel. The power dissipation is 47.64 ㎽/1ch.

A Highly Linear, Small-Area Analog Front End With Gain and Offset Compensation for Automotive Capacitive Pressure Sensors in 0.35- m CMOS

This paper presents a wide-frequencyrange, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal S22 and S11 matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in 0.13 μm, 1-poly, 6-metal CMOS technology. The die area of the transceiver is 4 mm x 3 mm. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm². The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

This paper presents a 1.248 Gb/s ? 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is 0.01 μs the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 600 μm x 250 μm. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are 35.24 Ps p-p and 4.25 Ps rms respectively for HS-G2 mode.

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using 0.18 ㎜ BCD process with high power MOSFET options, and the die area is 1870 ㎜ x 1430 ㎜. The power consumption of the charge pump itself is 79.13 ㎽ when the output power is 415.45 ㎽ at the high voltage mode, while it is 20.097 ㎽ when the output power is 89.903 ㎽ at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.