Tomohiro Kubo

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

In this paper, the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-MOSFETs was directly evaluated. Using scanning tunneling microscopy (STM), it was clearly observed that the roughness of extension edges induced by gate LER strongly depended on the implanted dose, pockets, and coimplantations. Impurity diffusion suppressed by a nitrogen (N) coimplant enhanced the roughness of the extension edges, which caused fluctuations in the device performance. The expected effect based on the carrier profiles measured by STM of the N coimplant on the electrical performance of the n-MOSFETs was verified

Ultra-low contact resistance for deca-nm MOSFETs by laser annealing

We demonstrate an ultra-low contact resistance of 4/spl times/10/sup -8/ /spl Omega/-cm/sup 2/ (5/spl times/ lower than RTA) using a laser annealing (LA) process. The contact resistance reduction is attributed to the high activated dopant concentration of 10/sup 21/ cm/sup -3/. For the first time, we have successfully fabricated LA-pMOSFETs with a conventional CMOS integration flow for lowering contact resistance.

Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs

The effects of shallow-trench isolation (STI) on the carrier profile of the extension region in sub-50-nm n-MOSFET were directly measured for the first time. The extension overlap length drastically decreased by 3 run within a distance from STI (Y) of 50 nm. In contrast, the channel concentration gradually increased within Y of 100 nm. The STI effect was also measured for transistors with a gate width of less than 130 nm in 6T-SRAM cell. Reduction of the STI effect by nitrogen co-implant suppressed sub-threshold leakage current by up to an order of magnitude and decreased fluctuation in the threshold voltage by 8 %.

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)

First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing

We report, for the first time, a detailed study of the 100 mum-scaled emissivity and temperature variation in millisecond annealing (MSA) depending on the Si trench structure, the shallow trench isolation (STI) structure, and transistor structure measured by Thermawave method. Flash lamp annealing (FLA) was applied as MSA technique. In case of Si trench structure with varying the trench depth, the relation between the trench depth and emissivity was clarified quantitatively. It was found that micro temperature variation within a chip driven by the emissivity variation exceeds of 100degC as the transistor structure was annealed by FLA.

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (Ion) for PMOS / NMOS, and Ion = 750(P) / 1030(N) [muA/mum] for Ioff = 100 [nA/mum] at Vdd= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.

Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain extension (SDE) resistance achieves a 15% improvement in the saturation on-current (I _on) at a 28-nm gate length for PMOS. A reduction in the source-dram parasitic resistance enables an over 50% improvement in the linear on-current (I_dlin) by capping layer stress on the 29-nm gate length, which is about a 10% increase in the I_dlin improvement ratio compared to that of the control device, and a 28% of I _on enhancement gave us I_on= 460 muA/mum for I _off= 100 nA/mum at V_d= -1.0 V. For NMOS, low resistance SDE can be obtained without inducing the deterioration of the V_th-rolloff thanks to the halo profile modulation, and 6% of I_on enhancement was achieved at a 29-nm gate length, and I _on= 925 muA/mum for I_off= 100 nA/mum at V _d= 1.0 V was obtained

Total temperature fluctuation of a patternned wafer in the millisecond annealing

This paper describes the total temperature fluctuation within patterned wafers based on sub-100μm-scaled microscopic temperature non-uniformity within a chip, and mm-scaled macroscopic temperature variation within blanket wafers in laser spike annealing (LSA) and Flash Lamp Annealing (FLA). Temperature distribution within a chip and non-uniformity within blanket wafers are obtained by thermal wave (TW) method and conventional 4 point probe sheet resistance measurement, respectively. In the case of LSA, it was found that the local temperature is less dependent on pattern density. However, hot spots which local temperature is 50 °C higher than the surrounding area occur near large active areas. In the case of FLA, the local temperature depends strongly on pattern pitch. We did not find the hot spot. Total temperature fluctuations of pattern wafers of LSA and FLA reach about 90 and 120 °C.