K. Shinotani

Liquid crystal polymers (LCP) for high performance SOP applications

Electronic devices will increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion preferably close to silicon, higher modulus, lower permittivity & loss, lower moisture absorption, better thermal conductivity, good dimensional stability, and more importantly reduced warpage particularly after the build-up process. The thermal properties of LCPs have led to increasing interest for the packaging community. This work deals with the evaluation of LCPs for future electronic packaging applications. LCP samples obtained from industry were analyzed using TA instruments. The samples with the properties best matched to the needs of future electronic packaging applications will be chosen based on the thermal analysis data presented for (i) fabrication of a base substrate using solely reinforced LCP, (ii) evaluating LCP for use as a carrier film, (iii) performing laser ablation techniques for via formation in the build up layers, and (iv) plating of the vias and the films for through hole Z-direction connections and X, Y, signal lines. In the present work, application of LCP as a dielectric layer for the system-on-package process has been evaluated. It is expected that the reinforced LCP films can also be utilized as a substrate material thereby providing the unique opportunity for superior compatibility between the substrate and the dielectric layer.

Selection and evaluation of materials for future system-on-package (SOP) substrate

This work deals with the selection and evaluation of candidate materials as a future base substrate for SOP. New composite materials using advanced fiber clothes and fillers were fabricated and tested to evaluate the increase in performance compared to conventional glass-epoxy substrates (FR-4). Composites built with advanced carbon-cloth having a negative thermal expansion coefficient (CTE) yielded a composite CTE of <3 ppm//spl deg/C. The composites have 2-3 times higher modulus than conventional FR-4. In order to evaluate materials with further higher modulus, metal matrix composites Al/SiC with low CTE of 7 ppm//spl deg/C and high modulus of 220 GPa were also considered. The thermomechanical reliability of the electrical interconnections was evaluated after assembling flip-chips on three different substrates by subjecting test vehicles to thermal shock treatments. The failure modes in different substrates were analyzed with optical microscopy. The stresses in the solder joints and dielectric layer were also estimated with analytical and finite element models (FEM).

Evaluation of liquid crystal polymers for high performance SOP application

Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.

The role of stiff base substrates in warpage reduction for future high-density-wiring requirements

The role of warpage on future high density wiring requirements is investigated. These studies also show the impact of the gap between mask and the substrate arising out of warpage on the width of fine lines when vacuum cannot reduce the effect of warpage. For 100 micron wide lines, substrates with warpage greater then 50 microns are found to result in 30% error in the actual transferred pattern, while warpage greater than 200 microns results in the complete elimination of photoresist openings. The via-pad misalignment for a 300 mm substrate was measured to be 116 microns for FR4 substrate while the value is less than 25 microns for AlN. The % displacement, defined as the distance between the via center and pad center normalized with respect to the pad diameter, is hence more than 25% in case of a warped substrate, while it is found to be less than 10% for stiffer substrates. Hence, as feature size becomes smaller, accurate translation of mask features on to the substrate during photolithography will be limited by the warpage of the substrate and hence stiffer substrates are required to meet next-generation high-density wiring needs.

In-situ stress and warpage measurements to investigate reliability of flip-chip on board assembly without underfill

Current printed wiring boards (PWBs) are all organic, the most common being epoxy-glass laminate FR-4 due to its cost effectiveness and overall perfonnance. However, for highdensity wiring (HDW) and assembly of flip-chips directly to the substrate without the use of underfill, substrate materials with low CTE and high elastic modulus are needed. Novel low CTE-high stiffness organic and inorganic hoards have been evaluated for flip-chip on board technology without the use of underfill. Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials and failure modes were characterized. In-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection. The effect of interlayer dielectric thickness on the package reliability has also been studied. The reliability test results are in accordance with the inferences from the in-situ warpage and stress measurements and it can be concluded that along with low CTE, high modulus is an inevitable substrate property requirement for flip-chip reliability without underfill in next-generation packages. This paper also presents Photostimulated Luminescence Spectroscopy (PSLS) and Raman Spectroscopy as non-destructive and direct techniques for the in-situ and residual stress measurement in microsystems and thus a powerful means for reliability assessment. Experimental results have also been supported by finite element models and analytical solutions.

Delamination issues in integration of highly filled polymer-ceramic nanocomposite films on MCM-L compatible substrates

The National Electronics Manufacturing Technology roadmap indicates that a capacitance density of 50 nF/cm/sup 2/ will be required in 2001 for successful implementation of integral passive technology. Polymer-ceramic composites are a favorable choice for thin-film capacitors in low-temperature MCM-L technology. Improvement in dielectric properties of the material, achievement of thin and defect-free films and integration on to large area substrates form the cornerstones for this technology. The Packaging Research Center at Georgia Tech. has been actively involved in achieving improved dielectric properties by developing high solids loading and well-dispersed suspensions based on colloidal techniques. The integration of thin-film composites into the subsequent fabrication process becomes increasingly challenging with higher filler content. For example, delamination of the composite from the bottom copper layer has been consistently observed during the modification of composite surface for increasing the adhesion between the electroless copper deposit (top electrode) and composite surface. The surface modification typically involves an etch-treatment with a powerful oxidizing agent such as permanganate. This delamination was not observed in fully cured neat epoxies. The role of fillers in preventing the curing of the epoxy, the reactions between permanganate and uncured epoxy and the lack of adhesion between ceramic and bottom electrode are some of the key issues involved in this delamination problem. This is further complicated by the classic copper-epoxy de-adhesion problem originating from the copper oxide film at the copper-epoxy interface. This work presents our investigation of the origin of this delamination problem by delineating these issues and identifying the key effects. In particular, the role of epoxy curing and filler content based on the interface and epoxy characterization is addressed here. A failure mechanism is proposed from the correlation between epoxy cure and the delamination during etch treatment.

Evaluation of low stress dielectrics for board application

The objective of this research is to evaluate and qualify low stress dielectric materials for multi-layer sequential buildup process. It is expected that a low CTE dielectric, such as Liquid Crystal Polymer (LCP), or a low modulus dielectric, such as ABSORE30NDTM will reduce the dielectric film stress generated due to CTE mismatch between the substrate and the dielectric layer. These dielectrics were laminated onto 3 board samples: carbon cyanate ester, carbon epoxy, and double-treated FR4. Atomic Force Microscope (AFM) was used to determine the surface roughness of various boards. Peel strength measurement was performed to quantify the adhesion between the dielectric and the board. Test beds were assembled using PB8 flip chips for thermo-mechanical reliability assessment.

Reliability assessment of high density multi-layer board assembly using shadow Moire and luminescence spectroscopy

Novel low CTE-high stiffness organic and inorganic boards were evaluated for flip-chip on board technology without underfill. Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials and failure modes were characterized. In-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection. The effect of interlayer dielectric thickness on the package reliability has also been studied. The reliability test results are in accordance with the inferences from the in-situ warpage and stress measurements and it can be concluded that along with low CTE, high modulus is an inevitable substrate property requirement for flip-chip reliability without underfill in next-generation packages. This paper also presents photostimulated luminescence spectroscopy as a nondestructive and direct technique for the in-situ stress measurement in microsystems and thus a powerful means for reliability assessment.